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公开(公告)号：US08080464B2
公开(公告)日：2011-12-20
申请号：US12971788
申请日：2010-12-17
IPC分类号： H01L21/30
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0262 , H01L21/02658 , H01L21/7624
摘要： Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.
摘要翻译： 提供了用于在绝缘体上的结构上蚀刻和/或沉积外延层的方法，该外延硅结构包括处理晶片，硅层和处理晶片和硅层之间的电介质层。 硅层具有限定结构的外表面的切割表面。 然后蚀刻晶片的切割表面，同时控制反应器的温度，使得蚀刻反应在动力学上受到限制。 然后在晶片上沉积外延层，同时控制反应器的温度，使得在切割表面上的沉积速率在动力学上受到限制。
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公开(公告)号：US20110159668A1
公开(公告)日：2011-06-30
申请号：US12971788
申请日：2010-12-17
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0262 , H01L21/02658 , H01L21/7624
摘要： Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.
摘要翻译： 提供了用于在绝缘体上的结构上蚀刻和/或沉积外延层的方法，该外延硅结构包括处理晶片，硅层和处理晶片和硅层之间的电介质层。 硅层具有限定结构的外表面的切割表面。 然后蚀刻晶片的切割表面，同时控制反应器的温度，使得蚀刻反应在动力学上受到限制。 然后在晶片上沉积外延层，同时控制反应器的温度，使得在切割表面上的沉积速率在动力学上受到限制。
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