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公开(公告)号：US20110159668A1
公开(公告)日：2011-06-30
申请号：US12971788
申请日：2010-12-17
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0262 , H01L21/02658 , H01L21/7624
摘要： Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.
摘要翻译： 提供了用于在绝缘体上的结构上蚀刻和/或沉积外延层的方法，该外延硅结构包括处理晶片，硅层和处理晶片和硅层之间的电介质层。 硅层具有限定结构的外表面的切割表面。 然后蚀刻晶片的切割表面，同时控制反应器的温度，使得蚀刻反应在动力学上受到限制。 然后在晶片上沉积外延层，同时控制反应器的温度，使得在切割表面上的沉积速率在动力学上受到限制。
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公开(公告)号：US08080464B2
公开(公告)日：2011-12-20
申请号：US12971788
申请日：2010-12-17
IPC分类号： H01L21/30
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0262 , H01L21/02658 , H01L21/7624
摘要： Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.
摘要翻译： 提供了用于在绝缘体上的结构上蚀刻和/或沉积外延层的方法，该外延硅结构包括处理晶片，硅层和处理晶片和硅层之间的电介质层。 硅层具有限定结构的外表面的切割表面。 然后蚀刻晶片的切割表面，同时控制反应器的温度，使得蚀刻反应在动力学上受到限制。 然后在晶片上沉积外延层，同时控制反应器的温度，使得在切割表面上的沉积速率在动力学上受到限制。
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公开(公告)号：US20110148128A1
公开(公告)日：2011-06-23
申请号：US12645565
申请日：2009-12-23
IPC分类号： H01L21/677 , B25J15/06
CPC分类号： H01L21/6838
摘要： A system and a wand are disclosed for the transport of a semiconductor wafer. The system and wand include a plate and a locator. The plate includes a plurality of plate outlets for directing gas flow against the wafer to hold the wafer using the Bernoulli principle. The locator extends from the plate and includes a locating outlet for directing a gas flow to locate the wafer laterally relative to the plate. The plate outlets and the locating outlet operate to prevent the wafer from contacting the plate or the locator. In some embodiments, a plurality of locators are used to locate the wafer laterally relative to the plate.
摘要翻译： 公开了用于输送半导体晶片的系统和棒。 系统和魔杖包括板和定位器。 该板包括多个板出口，用于使用伯努利原理将气流引向晶片以保持晶片。 定位器从板延伸并且包括用于引导气流以相对于板横向定位晶片的定位出口。 板出口和定位出口用于防止晶片接触板或定位器。 在一些实施例中，使用多个定位器来相对于板横向定位晶片。
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4.发明授权Thermal annealing process for producing silicon wafers with improved surface characteristics 有权用于生产具有改进的表面特性的硅晶片的热退火工艺公开(公告)号：US06743495B2
公开(公告)日：2004-06-01
申请号：US10113378
申请日：2002-03-29
IPC分类号： H01L2906
CPC分类号： H01L21/02046 , C30B29/06 , C30B33/00 , H01L21/02049 , H01L21/324 , Y10T428/21
摘要： A process for manufacturing silicon wafers that reduces the size of silicon wafer surface and/or sub-surface defects without the forming excessive haze. The process entails cleaning the front surface of the silicon wafer at a temperature of at least about 1100° C. by exposing the front surface to a cleaning ambient comprising H2, HF gas, or HCl gas to remove silicon oxide from the front surface and exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100° C. to a vacuum or an annealing ambient consisting essentially of a mono-atomic noble gas selected from the group consisting of He, Ne, Ar, Kr, and Xe to facilitate the migration of silicon atoms to the exposed agglomerated defects without substantially etching silicon from the front surface of the heated silicon wafer.
摘要翻译： 制造硅晶片的方法，其减小硅晶片表面和/或次表面缺陷的尺寸，而不会形成过大的雾度。 该方法需要在至少约1100℃的温度下清洁硅晶片的前表面，通过将前表面暴露于包括H 2，HF气体或HCl气体的清洁环境中以从前表面去除氧化硅并暴露 在至少约1100℃的温度下清洁的硅晶片的前表面至基本上由选自He，Ne，Ar，Kr的单原子惰性气体的真空或退火环境，以及 Xe以促进硅原子迁移到暴露的聚集的缺陷，而基本上不从加热的硅晶片的前表面蚀刻硅。
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5.发明授权Wafer holder for supporting a semiconductor wafer during a thermal treatment process 有权用于在热处理过程中支撑半导体晶片的晶片保持器公开(公告)号：US08186661B2
公开(公告)日：2012-05-29
申请号：US12211516
申请日：2008-09-16
申请人： John A. Pitney , Thomas A. Torack
发明人： John A. Pitney , Thomas A. Torack
IPC分类号： B25B1/24
CPC分类号： H01L21/6875 , Y10S269/90 , Y10S269/903
摘要： A wafer holder for holding a semiconductor wafer during a thermal wafer treatment process. The wafer holder includes at least three wafer supports. Each wafer support includes an upright shaft and a plurality of flexible fibers supported by the shaft in positions such that at least some of the fibers engage the semiconductor wafer when the wafer rests on the wafer supports.
摘要翻译： 一种用于在热晶片处理过程中保持半导体晶片的晶片保持器。 晶片保持器包括至少三个晶片支架。 每个晶片支撑件包括直立轴和由轴支撑的多个柔性纤维，使得当晶片搁置在晶片支架上时，至少一些光纤接合半导体晶片。
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6.发明申请WAFER HOLDER FOR SUPPORTING A SEMICONDUCTOR WAFER DURING A THERMAL TREATMENT PROCESS 有权用于在热处理过程中支持半导体波形的支架公开(公告)号：US20100065696A1
公开(公告)日：2010-03-18
申请号：US12211516
申请日：2008-09-16
申请人： John A. Pitney , Thomas A. Torack
发明人： John A. Pitney , Thomas A. Torack
CPC分类号： H01L21/6875 , Y10S269/90 , Y10S269/903
摘要： A wafer holder for holding a semiconductor wafer during a thermal wafer treatment process. The wafer holder includes at least three wafer supports. Each wafer support includes an upright shaft and a plurality of flexible fibers supported by the shaft in positions such that at least some of the fibers engage the semiconductor wafer when the wafer rests on the wafer supports.
摘要翻译： 一种用于在热晶片处理过程中保持半导体晶片的晶片保持器。 晶片保持器包括至少三个晶片支架。 每个晶片支撑件包括直立轴和由轴支撑的多个柔性纤维，使得当晶片搁置在晶片支架上时，至少一些光纤接合半导体晶片。
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公开(公告)号：US20080314319A1
公开(公告)日：2008-12-25
申请号：US11965506
申请日：2007-12-27
IPC分类号： C23C16/00
CPC分类号： H01L21/68735 , C23C16/4583 , C30B25/12 , H01L21/68742
摘要： A susceptor for supporting a semiconductor wafer in a heated chamber having an interior space. The susceptor includes a body having an upper surface and a lower surface opposite the upper surface. The susceptor also has a recess extending downward from the upper surface into the body along an imaginary central axis. The recess is sized and shaped for receiving the semiconductor wafer therein. The susceptor includes a plurality of lift pin openings extending through the body from the recess to the lower surface. Each of the lift pin openings is sized for accepting lift pins to selectively lift and lower the wafer with respect to the recess. The susceptor has a central opening extending through the body along the central axis from the recess to the lower surface.
摘要翻译： 一种用于在具有内部空间的加热室中支撑半导体晶片的感受体。 感受体包括具有与上表面相对的上表面和下表面的主体。 基座还具有沿着假想的中心轴线从上表面向下延伸到主体中的凹部。 凹部的尺寸和形状用于在其中接收半导体晶片。 基座包括从凹部延伸穿过主体到下表面的多个提升销开口。 每个提升销开口的尺寸适于接受提升销，以相对于凹部选择性地提升和降低晶片。 基座具有中心开口，该中心开口沿着中心轴线延伸穿过主体从凹部到下表面。
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公开(公告)号：US6086678A
公开(公告)日：2000-07-11
申请号：US262417
申请日：1999-03-04
IPC分类号： H01L21/00 , H01L21/677 , C23C16/00
CPC分类号： H01L21/67748 , H01L21/67017
摘要： A system for equalizing pressure across a gate adapted to selectively block a port connecting a wafer handling chamber to a process chamber of a reactor for depositing an epitaxial layer on a semiconductor wafer positioned in the process chamber. The system comprises a bypass passage connecting the process chamber to the wafer handling chamber for transporting gas between the process chamber and the wafer handling chamber when the gate is blocking the port connecting the wafer handling chamber to the process chamber of the reactor for equalizing pressure between the process chamber and the wafer handling chamber. The system also includes a bypass valve positioned along the bypass passage for selectively controlling gas flow through the bypass passage. The bypass valve has an open position in which gas is permitted to flow through the bypass passage to equalize pressure between the process chamber and the wafer handling chamber and a closed position in which gas is prevented from flowing through the bypass passage to isolate the process chamber from the wafer handling chamber. In addition, the system includes a flow restrictor positioned along the bypass passage for restricting gas flow through the bypass passage to limit pressure change rates in the process chamber and the wafer handling chamber when the bypass valve is in the open position and thereby to limit a maximum velocity of gas flowing through the bypass passage.
摘要翻译： 一种用于均衡跨过闸门的压力的系统，其适于选择性地阻挡将晶片处理室连接到反应器的处理室的端口，用于在位于处理室中的半导体晶片上沉积外延层。 该系统包括将处理室连接到晶片处理室的旁通通道，用于在处理室和晶片处理室之间输送气体，当栅极阻塞将晶片处理室连接到反应器的处理室的端口时， 处理室和晶片处理室。 该系统还包括沿旁路通道定位的旁通阀，用于选择性地控制通过旁路通道的气流。 旁通阀具有打开位置，在该位置允许气体流过旁路通道以均衡处理室和晶片处理室之间的压力，并且阻止气体流过旁路通道以隔离处理室的关闭位置 从晶片处理室。 此外，该系统包括沿着旁路通道定位的限流器，用于限制通过旁路通道的气流，以限制旁通阀处于打开位置时处理室和晶片处理室中的压力变化率，从而限制 流过旁路通道的气体的最大速度。
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公开(公告)号：US5891250A
公开(公告)日：1999-04-06
申请号：US72564
申请日：1998-05-05
IPC分类号： C23C16/44 , C23C16/455 , C30B25/14 , H01L21/205 , C23C16/00
CPC分类号： C23C16/455 , C30B25/14
摘要： A reactor for depositing an epitaxial layer on a semiconductor wafer contained within the reactor during a chemical vapor deposition process. The reactor comprises a reaction chamber sized and shaped for receiving a semiconductor wafer and an inlet passage in communication with the reaction chamber for delivering reactant gas to the reaction chamber. In addition the reactor includes a susceptor positioned in the reaction chamber for supporting the semiconductor wafer during the chemical vapor deposition process. Further, the reactor comprises an injector including a metering plate generally blocking reactant gas flow through the inlet passage. The plate has a slot extending through the plate totally within a periphery of the plate. The slot is sized for selectively restricting reactant gas flow past the plate thereby to meter reactant gas delivery to the chamber.
摘要翻译： 一种用于在化学气相沉积工艺期间在反应器内包含的半导体晶片上沉积外延层的反应器。 反应器包括反应室，其尺寸和形状用于接收半导体晶片和与反应室连通的入口通道，用于将反应气体输送到反应室。 此外，反应器包括位于反应室中的基座，用于在化学气相沉积工艺期间支撑半导体晶片。 此外，反应器包括喷射器，该喷射器包括通常阻挡通过入口通道的反应气流的计量盘。 该板具有在板的周边内完全延伸穿过该板的槽。 槽的尺寸用于选择性地限制反应物气体流过板，从而计量反应物气体输送到室。
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