公开(公告)号：US20100301395A1

公开(公告)日：2010-12-02

申请号：US12462515

申请日：2009-08-05

Applicant: Dong Xu ,  Xiaoping Yang ,  Wendell Kong ,  Lee M. Mohnkern ,  Phillip M. Smith ,  Pane-chane Chao

Inventor： Dong Xu ,  Xiaoping Yang ,  Wendell Kong ,  Lee M. Mohnkern ,  Phillip M. Smith ,  Pane-chane Chao

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/66431 ,  H01L29/7784 ,  H01L29/7785

Abstract: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.

Abstract translation: 高功率和高增益超短栅极HEMT器件具有特别的增益和由栅极电极的增加宽度不对称凹槽提供的异常高的击穿电压，通过复合沟道层，其包括嵌入在铟中的薄的砷化铟层 砷化镓沟道层，并通过使用额外的硅掺杂尖峰进行双掺杂。 改进的晶体管在110 GHz时具有超强的14 dB增益，并具有极高的3.5-4 V击穿电压，从而在超短栅极器件中提供高增益，大功率和超高频。

公开(公告)号：US08445941B2

公开(公告)日：2013-05-21

申请号：US12462515

申请日：2009-08-05

Applicant: Dong Xu ,  Xiaoping S. Yang ,  Wendell Kong ,  Lee M. Mohnkern ,  Phillip M. Smith ,  Pane-chane Chao

Inventor： Dong Xu ,  Xiaoping S. Yang ,  Wendell Kong ,  Lee M. Mohnkern ,  Phillip M. Smith ,  Pane-chane Chao

IPC: H01L21/335 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L29/7784 ,  H01L29/7785

Abstract: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.

公开(公告)号：US5454885A

公开(公告)日：1995-10-03

申请号：US170708

申请日：1993-12-21

Applicant: Gregory K. Dudoff ,  Karl A. Harris ,  Lee M. Mohnkern ,  Richard J. Williams ,  Robert W. Yanka ,  Thomas H. Meyers, III

Inventor： Gregory K. Dudoff ,  Karl A. Harris ,  Lee M. Mohnkern ,  Richard J. Williams ,  Robert W. Yanka ,  Thomas H. Meyers, III

IPC: H01L21/477 ,  H01L21/00 ,  H01L21/324

CPC classification number: H01L21/477 ,  Y10S148/063 ,  Y10S148/064

Abstract: A typical source of cadmium and tellurium is as a by-product of copper mining. Although attempts are made to remove impurities such as copper prior to commercially supplying them for forming material like cadmium telluride, cadmium zinc telluride and cadmium telluride selenide for use as a substrate to support electronic circuitry, processing during formation of the circuitry causes the impurities from the substrate to segregate into the circuitry, resulting in unacceptable electrical performance of the circuitry. A method for purifying the substrate prior to circuitry formation includes forming a sacrificial layer of mercury telluride or mercury cadmium telluride on the substrate, annealing the combination at elevated temperature with an overpressure of mercury and removing the sacrificial layer along with a contiguous portion of the substrate, if desired. The sacrificial layer may be formed by vapor phase type processes or even by liquid phase epitaxy.

Abstract translation: 镉和碲的典型来源是铜矿开采的副产品。 尽管在商业供应它们用于形成诸如碲化镉的材料，碲化镉锌和碲化镉硒化物作为基板以支持电子电路之前，尝试去除诸如铜的杂质，但是在形成电路期间的处理会导致来自 衬底分离到电路中，导致电路的不可接受的电性能。 用于在电路形成之前净化衬底的方法包括在衬底上形成汞碲化物或碲化汞镉的牺牲层，在高压下用汞过压退火组合，并与衬底的连续部分一起去除牺牲层 如果需要的话。 牺牲层可以通过气相法或液相外延形成。