Asymmetrically recessed high-power and high-gain ultra-short gate HEMT device
    2.
    发明申请
    Asymmetrically recessed high-power and high-gain ultra-short gate HEMT device 有权
    不对称凹陷的大功率和高增益超短栅HEMT器件

    公开(公告)号:US20100301395A1

    公开(公告)日:2010-12-02

    申请号:US12462515

    申请日:2009-08-05

    IPC分类号: H01L29/778 H01L21/335

    摘要: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.

    摘要翻译: 高功率和高增益超短栅极HEMT器件具有特别的增益和由栅极电极的增加宽度不对称凹槽提供的异常高的击穿电压,通过复合沟道层,其包括嵌入在铟中的薄的砷化铟层 砷化镓沟道层,并通过使用额外的硅掺杂尖峰进行双掺杂。 改进的晶体管在110 GHz时具有超强的14 dB增益,并具有极高的3.5-4 V击穿电压,从而在超短栅极器件中提供高增益,大功率和超高频。

    Reproducible, high yield method for fabricating ultra-short T-gates on HFETs
    3.
    发明申请
    Reproducible, high yield method for fabricating ultra-short T-gates on HFETs 有权
    用于在HFET上制造超短T型栅极的可再现的高产率方法

    公开(公告)号:US20080241757A1

    公开(公告)日:2008-10-02

    申请号:US12079529

    申请日:2008-03-27

    IPC分类号: G03F7/20

    CPC分类号: H01L21/28581 H01L21/0272

    摘要: A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.

    摘要翻译: 一种用于在异质结场效应晶体管(HFET)上制造超短T栅极的方法,包括以下步骤:(a)提供三层抗蚀剂的涂层与底部具有高分子量的聚甲基丙烯酸甲酯(PMMA),聚二甲基戊二酰亚胺(PMGI ),顶部分子量低的PMMA; (b)在第一次曝光中,用一定剂量的显影剂曝光和显影层,以使得显影剂能够破坏顶部PMMA但是低,以避免对底部PMMA层中所接收的总剂量产生显着影响; 和(c)在第二次曝光中,使用曝光和显影过程在底部PMMA层中限定0.03-0.05μm的开口。

    Reproducible, high yield method for fabricating ultra-short T-gates on HFETs
    4.
    发明授权
    Reproducible, high yield method for fabricating ultra-short T-gates on HFETs 有权
    用于在HFET上制造超短T型栅极的可再现的高产率方法

    公开(公告)号:US07943286B2

    公开(公告)日:2011-05-17

    申请号:US12079529

    申请日:2008-03-27

    IPC分类号: G03F7/26

    CPC分类号: H01L21/28581 H01L21/0272

    摘要: A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.

    摘要翻译: 一种用于在异质结场效应晶体管(HFET)上制造超短T栅极的方法,包括以下步骤:(a)提供三层抗蚀剂的涂层与底部具有高分子量的聚甲基丙烯酸甲酯(PMMA),聚二甲基戊二酰亚胺(PMGI ),顶部分子量低的PMMA; (b)在第一次曝光中,用一定剂量的显影剂曝光和显影层,以使得显影剂能够破坏顶部PMMA但是低,以避免对底部PMMA层中所接收的总剂量产生显着影响; 和(c)在第二次曝光中,使用曝光和显影过程在底部PMMA层中限定0.03-0.05μm的开口。