公开(公告)号：US20060261478A1

公开(公告)日：2006-11-23

申请号：US11421773

申请日：2006-06-02

申请人： Kong-Beng Thei ,  Chun-Lung Cheng ,  Hsi-Chien Lin ,  Li-Don Chen ,  Tung-Lung Lai ,  Chi-Lung Lin

发明人： Kong-Beng Thei ,  Chun-Lung Cheng ,  Hsi-Chien Lin ,  Li-Don Chen ,  Tung-Lung Lai ,  Chi-Lung Lin

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A barrier layer stack. The barrier layer stack includes a semiconductor process wafer comprising an exposed conductive region, a first barrier layer stack comprising at least one TiN and one Ti layers overlying and contacting the conductive region, wherein the TiN layer is contacted with the Ti layer, and an overlying aluminum alloy layer in contact with the first barrier layer stack.

摘要翻译： 阻挡层堆叠。 阻挡层堆叠包括包括暴露的导电区域的半导体工艺晶片，包括至少一个TiN的第一势垒层堆叠和覆盖并接触导电区域的一个Ti层，其中TiN层与Ti层接触，并且覆盖 铝合金层与第一阻挡层堆叠接触。

公开(公告)号：US07470992B2

公开(公告)日：2008-12-30

申请号：US11421773

申请日：2006-06-02

申请人： Kong-Beng Thei ,  Chun-Lung Cheng ,  Hsi-Chien Lin ,  Li-Don Chen ,  Tung-Lung Lai ,  Chi-Lung Lin

发明人： Kong-Beng Thei ,  Chun-Lung Cheng ,  Hsi-Chien Lin ,  Li-Don Chen ,  Tung-Lung Lai ,  Chi-Lung Lin

IPC分类号： H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A barrier layer stack. The barrier layer stack includes a semiconductor process wafer comprising an exposed conductive region, a first barrier layer stack comprising at least one TiN and one Ti layers overlying and contacting the conductive region, wherein the TiN layer is contacted with the Ti layer, and an overlying aluminum alloy layer in contact with the first barrier layer stack.

摘要翻译： 阻挡层堆叠。 阻挡层堆叠包括包括暴露的导电区域的半导体工艺晶片，包括至少一个TiN的第一势垒层堆叠和覆盖并接触导电区域的一个Ti层，其中TiN层与Ti层接触，并且覆盖 铝合金层与第一阻挡层堆叠接触。

公开(公告)号：US07064056B2

公开(公告)日：2006-06-20

申请号：US10460981

申请日：2003-06-13

申请人： Kong-Beng Thei ,  Chun-Lung Cheng ,  His-Chien Lin ,  Li-Don Chen ,  Tung-Lung Lai ,  Chi-Lung Lin

发明人： Kong-Beng Thei ,  Chun-Lung Cheng ,  His-Chien Lin ,  Li-Don Chen ,  Tung-Lung Lai ,  Chi-Lung Lin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved barrier layer stack and method for forming the same for preserving an aluminum alloy interconnect resistivity, the method comprising providing a semiconductor process wafer comprising an exposed conductive region; forming a first barrier layer comprising a barrier layer stack over the exposed conductive region comprising one of a TiN or Ti layer in contact with the conductive region; forming at least one additional barrier layer comprising the barrier layer stack to form an alternating sequence of TiN and Ti layers; forming an uppermost barrier layer of TiN comprising the barrier layer stack; forming an overlying aluminum alloy region in contact with the uppermost barrier layer; and, subjecting the semiconductor process wafer to at least one process comprising a temperature of greater than temperatures greater than about 350° C.

摘要翻译： 一种改进的阻挡层堆叠及其形成方法，用于保持铝合金互连电阻率，该方法包括提供包括暴露的导电区域的半导体工艺晶片; 在包括与所述导电区域接触的TiN或Ti层之一的所述暴露的导电区域上形成包含阻挡层叠层的第一阻挡层; 形成包含阻挡层叠层的至少一个附加阻挡层以形成TiN和Ti层的交替序列; 形成包含阻挡层叠层的最上层的TiN阻挡层; 形成与最上层阻挡层接触的上覆铝合金区域; 并且对半导体工艺晶片进行至少一种包括温度大于约350℃的温度的工艺。

公开(公告)号：US06194249B1

公开(公告)日：2001-02-27

申请号：US09431133

申请日：1999-11-01

申请人： Ming Hsien Chen ,  Mei-Yen Li ,  Li-Don Chen ,  Chih-Ming Chen

发明人： Ming Hsien Chen ,  Mei-Yen Li ,  Li-Don Chen ,  Chih-Ming Chen

IPC分类号： H01L2144

CPC分类号： H01L23/3192 ,  H01L23/3142 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： The invention offers a solution to several problems associated wit IC packages that use a top layer of molded plastic. This has been achieved by inter-posing a dummy layer of dielectric material between the upper surface of the integrated circuit wafer and the molded plastic layer. This dummy layer is patterned and etched so that its surface becomes an alternating series of valleys and ridges, care being taken to ensure that all wiring lines are protected by being within ridges. This structure serves both to protect the wiring lines during the application of the molded plastic and, because of the large surface area of contact between plastic and wafer, excellent adhesion of the molded plastic to the wafer is obtained.

摘要翻译： 本发明提供了与使用顶层模制塑料的IC封装相关的几个问题的解决方案。 这是通过在集成电路晶片的上表面和模制塑料层之间互相构造介电材料的虚设层来实现的。 该虚拟层被图案化和蚀刻，使得其表面变成一系列交替的谷和脊，注意确保所有的布线被脊部保护。 该结构既用于在模塑塑料的应用过程中保护布线，并且由于塑料和晶片之间的大的表面接触面积，所以获得了模塑塑料对晶片的优良粘接性。