公开(公告)号：US20130338959A1

公开(公告)日：2013-12-19

申请号：US13523895

申请日：2012-06-15

Applicant: YUN-PENG HO ,  Liang-Po Chen

Inventor： YUN-PENG HO ,  Liang-Po Chen

IPC: G06F19/00

CPC classification number: G06F11/22

Abstract: A switching-type categorizing and testing apparatus of a Radio Frequency integrated Circuit (RFIC) is used to test and categorize at least one RFIC module. The apparatus comprises at least one testing module and a plurality of categorizing modules. The testing module is used to test the RFIC module, and the categorizing modules comprise a first categorizing module and a second categorizing module. The testing module tests the RFIC module within one of the two categorizing modules at the same when the other categorizing module categorizes the RFIC module already tested. The present invention may further increase the testing and categorizing quantity so as to achieve the fast and cost-saving advantages.

Abstract translation: 使用射频集成电路（RFIC）的开关式分类和测试装置来测试和分类至少一个RFIC模块。 该装置包括至少一个测试模块和多个分类模块。 测试模块用于测试RFIC模块，并且分类模块包括第一分类模块和第二分类模块。 当其他分类模块对已经测试的RFIC模块进行分类时，测试模块将在两个分类模块之一内测试RFIC模块。 本发明可以进一步增加测试和分类数量，从而实现快速和节省成本的优点。

公开(公告)号：US5658806A

公开(公告)日：1997-08-19

申请号：US547715

申请日：1995-10-26

Applicant: Horng-Chih Lin ,  Liang-Po Chen ,  Hsiao-Yi Lin ,  Chun-Yen Chang

Inventor： Horng-Chih Lin ,  Liang-Po Chen ,  Hsiao-Yi Lin ,  Chun-Yen Chang

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/786 ,  H01L21/265 ,  H01L21/465

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/6675 ,  H01L29/66765 ,  H01L29/78648

Abstract: A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting layer, and a first dielectric layer are formed to cover the substrate and the gate dielectric layer. Afterwards, a chemical mechanical polishing process is applied to subsequently polish the first dielectric layer and the conducting layer to expose the semiconductor layer above the gate electrode. Therefore, the conducting layer disposed at opposite sides of the gate electrode is self-aligned to act as the source/drain regions of the fabricated TFT device.

Abstract translation: 根据本发明的制造自对准薄膜晶体管的方法首先包括在绝缘层上形成栅电极。 接下来，形成栅介电层以包围栅电极。 随后，形成半导体层，导电层和第一介电层以覆盖基板和栅极介电层。 然后，施加化学机械抛光工艺以随后抛光第一介电层和导电层，以露出栅电极上方的半导体层。 因此，设置在栅电极的相对侧的导电层是自对准的，用作所制造的TFT器件的源/漏区。

公开(公告)号：US5913123A

公开(公告)日：1999-06-15

申请号：US912524

申请日：1997-08-18

Applicant: Horng-Chih Lin ,  Jien-Sheng Chao ,  Liang-Po Chen

Inventor： Horng-Chih Lin ,  Jien-Sheng Chao ,  Liang-Po Chen

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/22

CPC classification number: H01L29/6659 ,  H01L21/2254 ,  H01L21/2652

Abstract: A method for manufacturing a deep-submicron P-type metal-oxide semiconductor shallow junction utilizes an electron terminal structure with a base covered by a layer containing boron, germanium, and silicon. This layer containing boron, germanium, and silicon ("B--Ge--Si") is used as a shield during ion implanting and as an impurity ion source to form a high diffusion ion concentration at a shallow junction of the semiconductor base or substrate. The B--Ge--Si layer can be thoroughly removed using selective corrosive erosion. Due to the simplicity of this invention's manufacturing process, it can be used for deep-submicron PMOS component production, and thus, it has great practical value.

Abstract translation: 用于制造深亚微米P型金属氧化物半导体浅结的方法利用具有由包含硼，锗和硅的层覆盖的基底的电子端子结构。 在离子注入期间使用含有硼，锗和硅（“B-Ge-Si”）的层作为杂质离子源，以在半导体基底或衬底的浅结处形成高扩散离子浓度。 可以使用选择性腐蚀性侵蚀彻底去除B-Ge-Si层。 由于本发明的制造工艺简单，可用于深亚微米PMOS元件的生产，具有很大的实用价值。