公开(公告)号：US5913123A

公开(公告)日：1999-06-15

申请号：US912524

申请日：1997-08-18

Applicant: Horng-Chih Lin ,  Jien-Sheng Chao ,  Liang-Po Chen

Inventor： Horng-Chih Lin ,  Jien-Sheng Chao ,  Liang-Po Chen

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/22

CPC classification number: H01L29/6659 ,  H01L21/2254 ,  H01L21/2652

Abstract: A method for manufacturing a deep-submicron P-type metal-oxide semiconductor shallow junction utilizes an electron terminal structure with a base covered by a layer containing boron, germanium, and silicon. This layer containing boron, germanium, and silicon ("B--Ge--Si") is used as a shield during ion implanting and as an impurity ion source to form a high diffusion ion concentration at a shallow junction of the semiconductor base or substrate. The B--Ge--Si layer can be thoroughly removed using selective corrosive erosion. Due to the simplicity of this invention's manufacturing process, it can be used for deep-submicron PMOS component production, and thus, it has great practical value.

Abstract translation: 用于制造深亚微米P型金属氧化物半导体浅结的方法利用具有由包含硼，锗和硅的层覆盖的基底的电子端子结构。 在离子注入期间使用含有硼，锗和硅（“B-Ge-Si”）的层作为杂质离子源，以在半导体基底或衬底的浅结处形成高扩散离子浓度。 可以使用选择性腐蚀性侵蚀彻底去除B-Ge-Si层。 由于本发明的制造工艺简单，可用于深亚微米PMOS元件的生产，具有很大的实用价值。

公开(公告)号：US20080006908A1

公开(公告)日：2008-01-10

申请号：US11483906

申请日：2006-07-10

Applicant: Hong-Nien Lin ,  Horng-Chih Lin ,  Tiao-Yuan Huang

Inventor： Hong-Nien Lin ,  Horng-Chih Lin ,  Tiao-Yuan Huang

IPC: H01L29/06 ,  H01L31/00

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/7851 ,  H01L29/78687

Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

Abstract translation: 公开了鳍FET或其他多栅极晶体管。 晶体管包括具有第一晶格常数的半导体衬底和从半导体衬底延伸的半导体鳍片。 翅片具有与第一晶格常数不同的第二晶格常数以及顶表面和两个相对的侧表面。 晶体管还包括覆盖所述顶表面和所述两个相对侧表面的至少一部分的栅极电介质，以及覆盖所述栅极电介质的至少一部分的栅电极。 所得到的通道具有由翅片和衬底之间的晶格失配引起的应变。 可以通过选择相应的材料来调节该应变。

公开(公告)号：US20070267697A1

公开(公告)日：2007-11-22

申请号：US11470627

申请日：2006-09-07

Applicant: Huai-Yuan Tseng ,  Chen-Pang Kung ,  Horng-Chih Lin ,  Ming-Hsien Lee

Inventor： Huai-Yuan Tseng ,  Chen-Pang Kung ,  Horng-Chih Lin ,  Ming-Hsien Lee

IPC: H01L27/01

CPC classification number: H01L29/41733 ,  H01L29/78618

Abstract: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.

Abstract translation: 提供了包括绝缘基板的半导体器件的结构。 沟道层设置在绝缘基板上。 多个掺杂层设置在绝缘基板上并从沟道层突出。 掺杂层形成至少两个源极/漏极（S / D电极）对，并且每个S / D电极对相对于沟道层具有不同的延伸方向。 栅介质层设置在沟道层上。 栅极层设置在栅极介电层上。 优选地，例如，S / D电极对中的至少一个的延伸方向是第一方向，并且至少另一个S / D电极对的延伸方向是第二方向。

公开(公告)号：US06667508B2

公开(公告)日：2003-12-23

申请号：US10020916

申请日：2001-12-19

Applicant: Horng-Chih Lin ,  Tiao-Yuan Huang

Inventor： Horng-Chih Lin ,  Tiao-Yuan Huang

IPC: H01L29788

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/47 ,  H01L29/7885

Abstract: A novel structure of nonvolatile memory is formed on p type silicon and includes a stacked gate, a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the stacked gate has a source region and the other has a drain region, wherein the surface of the source region includes a thin metal silicide connected with a channel region to form a Schottky barrier. A tilted angle implant with As or P doping is performed on the p type silicon substrate to form a drain region and extend a portion of the drain region to a channel region under the stacked gate. For implanting, an n doped source region is also formed, creating an offset between the source region and the channel region as a result of the tilted angle implant. For programming, the source region is grounded, positive voltage is applied to the drain region and the gate, such that the hot carriers inject into the floating gate through the channel adjacent to the source region.

Abstract translation: 在p型硅上形成非易失性存储器的新颖结构，并且包括堆叠栅极，隧道电介质层，浮动栅极（FG），电介质层和控制栅极（CG）。 堆叠栅极的一侧具有源极区域，另一侧具有漏极区域，其中源极区域的表面包括与沟道区域连接以形成肖特基势垒的薄金属硅化物。 在p型硅衬底上执行具有As或P掺杂的倾斜角度注入以形成漏极区域，并且将漏极区域的一部分延伸到堆叠栅极下方的沟道区域。 对于注入，也形成了n掺杂的源极区域，由于倾斜角度注入的结果，在源极区域和沟道区域之间产生偏移。 对于编程，源极区域接地，正电压被施加到漏极区域和栅极，使得热载流子通过与源极区域相邻的沟道注入浮置栅极。

公开(公告)号：US5827768A

公开(公告)日：1998-10-27

申请号：US888765

申请日：1997-07-07

Applicant: Horng-Chih Lin ,  Tiao-yuan Huang

Inventor： Horng-Chih Lin ,  Tiao-yuan Huang

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/66575 ,  H01L21/76895 ,  H01L29/41775 ,  H01L21/2257 ,  H01L29/665

Abstract: A new method for manufacturing an MOS transistor is applied in the deep submicron process. In this method, a polysilicon layer is mainly used to form a raised source/drain structure and self-alignment is achieved by means of a planarization process. This method can reduce short channel effects and the series impedance of the source/drain as well as accomplish the local interconnection of a circuit and planarization. Therefore, this method is very suitable for manufacturing devices in the deep submicron process.

Abstract translation: 在深亚微米工艺中应用了一种用于制造MOS晶体管的新方法。 在该方法中，多晶硅层主要用于形成升高的源极/漏极结构，并且通过平坦化工艺实现自对准。 该方法可以减少源极/漏极的短沟道效应和串联阻抗，并实现电路的局部互连和平坦化。 因此，该方法非常适合于在深亚微米工艺中制造器件。

公开(公告)号：US07972912B2

公开(公告)日：2011-07-05

申请号：US12353236

申请日：2009-01-13

Applicant: Huai-Yuan Tseng ,  Chen-Pang Kung ,  Horng-Chih Lin ,  Ming-Hsien Lee

Inventor： Huai-Yuan Tseng ,  Chen-Pang Kung ,  Horng-Chih Lin ,  Ming-Hsien Lee

IPC: H01L21/00

CPC classification number: H01L29/41733 ,  H01L29/78618

Abstract: A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions.

Abstract translation: 制造半导体器件的方法包括：首先提供绝缘衬底。 图案化导电层形成在绝缘基板上，并且图案化导电层包括沟道区域和多个突出区域。 在绝缘基板上形成栅极结构层。 栅极结构层覆盖图案化导电层的一部分，并且每个突出区域具有暴露区域。 执行掺杂工艺以至少掺杂图案化导电层的暴露区域以形成多个S / D区域。

公开(公告)号：US20090130804A1

公开(公告)日：2009-05-21

申请号：US12353236

申请日：2009-01-13

Applicant: Huai-Yuan Tseng ,  Chen-Pang Kung ,  Horng-Chih Lin ,  Ming-Hsien Lee

Inventor： Huai-Yuan Tseng ,  Chen-Pang Kung ,  Horng-Chih Lin ,  Ming-Hsien Lee

IPC: H01L21/336

CPC classification number: H01L29/41733 ,  H01L29/78618

Abstract: A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions.

Abstract translation: 制造半导体器件的方法包括：首先提供绝缘衬底。 图案化导电层形成在绝缘基板上，并且图案化导电层包括沟道区域和多个突出区域。 在绝缘基板上形成栅极结构层。 栅极结构层覆盖图案化导电层的一部分，并且每个突出区域具有暴露区域。 执行掺杂工艺以至少掺杂图案化导电层的暴露区域以形成多个S / D区域。

公开(公告)号：US06495432B2

公开(公告)日：2002-12-17

申请号：US09834268

申请日：2001-04-12

Applicant: Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

Inventor： Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

IPC: H01L21336

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/823842

Abstract: A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, boron ions (B+) are doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to form a polysilicon gate. The gate photoresist is used as a mask to dope boron difluoride ions (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain region on the silicon substrate.

Abstract translation: 降低CMOS晶体管中的硼渗透的方法提供了一种硅衬底，其包括在有源层中的硅衬底上形成的隔离区，有源区和栅极氧化层。 然后在硅衬底上沉积多晶硅层。 接下来，将硼离子（B +）掺杂到多晶硅层中。 接下来，在多晶硅层上形成具有预定栅极图案的栅极光致抗蚀剂。 然后蚀刻未被栅极光致抗蚀剂覆盖的多晶硅以形成多晶硅栅极。 栅极光致抗蚀剂用作掩模以将二氟化硼离子（BF 2 +）掺杂到硅衬底中。 最后，在去除栅极光致抗蚀剂之后，进行回火处理以在硅衬底上形成源/漏区的浅结区。

公开(公告)号：US06432786B1

公开(公告)日：2002-08-13

申请号：US09829498

申请日：2001-04-09

Applicant: Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

Inventor： Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

IPC: H01L21425

Abstract: A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on the gate oxide layer. Next, a gate doping process and a fluorine ion implantation are performed on the polysilicon layer. Then, a high-temperature tempering procedure is performed to make the fluorine enter the gate oxide layer.

公开(公告)号：US06232206B1

公开(公告)日：2001-05-15

申请号：US09208409

申请日：1998-12-10

Applicant: Tiao-Yuan Huang ,  Horng-Chih Lin

Inventor： Tiao-Yuan Huang ,  Horng-Chih Lin

IPC: H01L21425

CPC classification number: H01L27/0251 ,  Y10S438/966

Abstract: A method is provided for selective oxidation on source/drain regions of transistors on an integrated circuit. The method includes the steps of a) incorporating a neutral species into first kind of the source/drain regions, and b) forming oxidation regions over the first kind of source/drain regions and second kind of the source/drain regions, wherein the oxidation regions over the second kind are thicker than the oxidation regions over the first kind.

Abstract translation: 提供了一种用于在集成电路上的晶体管的源极/漏极区域上进行选择性氧化的方法。 该方法包括以下步骤：a）将中性物质并入第一种源极/漏极区域，以及b）在第一种源极/漏极区域和第二种源极/漏极区域上形成氧化区域，其中氧化 第二类的区域比第一类的氧化区域厚。