公开(公告)号：US5036528A

公开(公告)日：1991-07-30

申请号：US471915

申请日：1990-01-29

申请人： Duc N. Le ,  Lordson L. Yue ,  Cirillo L. Costantino ,  David P. Chengson ,  Duc N. Le ,  Lordson L. Yue ,  Aurangzeb K. Khan

发明人： Duc N. Le ,  Lordson L. Yue ,  Cirillo L. Costantino ,  David P. Chengson ,  Duc N. Le ,  Lordson L. Yue ,  Aurangzeb K. Khan

IPC分类号： G06F1/12 ,  G06F1/10 ,  H03K5/00

CPC分类号： G06F1/10

摘要： The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

公开(公告)号：US07439988B1

公开(公告)日：2008-10-21

申请号：US11295200

申请日：2005-12-05

申请人： Vimal S. Parikh ,  Henry Packard Moreton ,  Lordson L. Yue

发明人： Vimal S. Parikh ,  Henry Packard Moreton ,  Lordson L. Yue

IPC分类号： G09G5/00

CPC分类号： G06T15/005 ,  G06T15/30

摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation that is defined with respect to a clipping plane. The clipping engine is configured to clip the graphics primitive with respect to the clipping plane based on the canonical representation.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，剪辑模块包括连接到映射单元的映射单元和剪辑引擎。 映射单元被配置为将图形基元映射到相对于剪切平面定义的规范表示。 剪辑引擎被配置为基于规范表示来相对于裁剪平面剪切图形原语。

公开(公告)号：US07224364B1

公开(公告)日：2007-05-29

申请号：US09244270

申请日：1999-02-03

申请人： Lordson L. Yue ,  James T. Battle

发明人： Lordson L. Yue ,  James T. Battle

IPC分类号： G06T11/00 ,  G06T11/20

CPC分类号： G06T15/005

摘要： A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.

摘要翻译： 帧缓冲器被划分为例如32×32像素的瓦片。 在给定瓦片内的三角形（及其部分）一次被一个三角形光栅化到瓦片位置。 该过程对于图像帧中的每个图块重复。 排序电路产生表示当前三角形的顶点的垂直顺序的控制位。 一系列多路复用器将这些控制位上的顶点垂直排列。 区域计算电路产生表示相对于当前瓦片的每个顶点的位置的区域位。 如果区域位指示整个三角形位于瓦片之外，则会发生三角形数据的平凡丢弃。 随后，基于区域比特来估计初始光栅化起始点，以降低光栅化器找到要分配值的当前三角形的第一像素所需的时间。

公开(公告)号：US4951050A

公开(公告)日：1990-08-21

申请号：US268422

申请日：1988-11-08

申请人： Aurangzeb K. Khan ,  Lordson L. Yue

发明人： Aurangzeb K. Khan ,  Lordson L. Yue

IPC分类号： H03M5/20

CPC分类号： H03M5/20

摘要： Encoding and decoding circuits, utilizing high speed ECL-like logic, simultaneously transmit and receive multiple binary signals via a single I/O pin.

摘要翻译： 使用高速ECL逻辑的编码和解码电路通过单个I / O引脚同时发送和接收多个二进制信号。

公开(公告)号：US07542046B1

公开(公告)日：2009-06-02

申请号：US11475599

申请日：2006-06-26

申请人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

发明人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

IPC分类号： G06F12/00

CPC分类号： G06T1/60

摘要： An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clipping unit, and an addressing unit that is connected to the read-only memory and the read-write memory. The read-only memory is configured to store a clipping program, and the read-write memory is configured to store a patch program. The addressing unit is configured to selectively address one of the read-only memory and the read-write memory based on a set of input conditions.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，图形处理装置包括剪切单元，连接到剪切单元的只读存储器，连接到剪切单元的读写存储器，以及连接到读取存储器的寻址单元， 只读存储器和读写存储器。 只读存储器被配置为存储剪切程序，并且读写存储器被配置为存储补丁程序。 寻址单元被配置为基于一组输入条件来选择性地寻址只读存储器和读写存储器中的一个。

公开(公告)号：US06393512B1

公开(公告)日：2002-05-21

申请号：US09407224

申请日：1999-09-27

申请人： Andrea Y. J. Chen ,  Lordson L. Yue

发明人： Andrea Y. J. Chen ,  Lordson L. Yue

IPC分类号： G06F1200

CPC分类号： G06F13/1647

摘要： A bank conflict detector compares at least a portion of a current address signal (i.e. an address signal generated by a request currently issued to main memory) with a corresponding portion of a to-be-issued memory address signal, to determine if a bank conflict exists. Specifically, in one embodiment, the bank conflict detector includes a number of exclusive OR gates that receive as inputs the two addresses to be compared, and generate an output (also called “XOR result”) that is compared with predetermined patterns to determine if a bank conflict exists. For example, if the bank conflict detector finds that the XOR result is 0 (zero) then the two addresses access the same bank. The bank conflict detector also the XOR result with patterns that are formed by a number of consecutive 1s in the least significant bits and a number of consecutive 0s in the most significant bits. If no match, then the bank conflict detector determines that no bank conflict exists. Otherwise, the bank conflict detector compares at least one of the addresses (both addresses in one implementation) with one or more predetermined patterns (e.g. two patterns in one implementation), and in case of a match determines that a bank conflict exists, and otherwise determines that no bank conflict exists. These patterns also have 0s in the least significant positions and 1s in the most significant positions or vice versa, depending on the implementation.

摘要翻译： 银行冲突检测器将当前地址信号的至少一部分（即，由当前发送到主存储器的请求产生的地址信号）与待发布的存储器地址信号的相应部分进行比较，以确定是否存在冲突 存在 具体来说，在一个实施例中，存储体冲突检测器包括多个异或门，其接收要比较的两个地址作为输入，并产生与预定模式进行比较的输出（也称为“异或结果”），以确定是否 存在银行冲突。 例如，如果存储体冲突检测器发现XOR结果为0（零），则两个地址访问同一个存储区。 银行冲突检测器还具有由最低有效位中的多个连续1形成的模式和最高有效位中的多个连续0的XOR结果。 如果没有匹配，则银行冲突检测器确定不存在银行冲突。 否则，银行冲突检测器将至少一个地址（一个实现中的两个地址）与一个或多个预定模式（例如，一个实现中的两个模式）进行比较，并且在匹配的情况下确定存在银行冲突，否则 决定不存在银行冲突。 这些模式在最低有效位置也有0，在最重要的位置也有1，反之亦然，这取决于实现。

公开(公告)号：US08432406B1

公开(公告)日：2013-04-30

申请号：US12182588

申请日：2008-07-30

申请人： Lordson L. Yue ,  Vimal S. Parikh

发明人： Lordson L. Yue ,  Vimal S. Parikh

IPC分类号： G06T1/20

CPC分类号： G09G5/363 ,  G06T1/20

摘要： An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to produce and issue ni initial outputs based on execution of a set of clipping operations, wherein ni represents the number of the initial outputs that are issued by the clipping unit prior to context switching, and the initial outputs partially define a clipped graphics primitive. The graphics processing apparatus also includes a control unit connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, wherein the initial execution state is preserved based on ni.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，图形处理装置包括剪辑单元，其被配置为基于执行一组剪切操作来产生和发出ni初始输出，其中ni表示由剪辑单元在之前发出的初始输出的数量 上下文切换，并且初始输出部分地限定剪切的图形原语。 图形处理装置还包括连接到裁剪单元的控制单元。 控制单元被配置为响应于用于上下文切换的初始命令来保留剪切单元的初始执行状态，其中基于ni来保留初始执行状态。

公开(公告)号：US07420572B1

公开(公告)日：2008-09-02

申请号：US11313085

申请日：2005-12-19

申请人： Lordson L. Yue ,  Vimal S. Parikh

发明人： Lordson L. Yue ,  Vimal S. Parikh

IPC分类号： G09G5/00 ,  G06T1/20

CPC分类号： G09G5/363 ,  G06T1/20

摘要： An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to issue an initial set of outputs based on execution of a set of clipping operations. The graphics processing apparatus also includes a control unit that is connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, and the initial execution state is preserved based on a number of the initial set of outputs.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，图形处理装置包括限幅单元，其被配置为基于一组剪切操作的执行来发出初始输出集合。 图形处理装置还包括连接到剪辑单元的控制单元。 控制单元被配置为响应于用于上下文切换的初始命令来保留剪切单元的初始执行状态，并且基于初始输出集合的数量来保留初始执行状态。

公开(公告)号：US07292254B1

公开(公告)日：2007-11-06

申请号：US11294791

申请日：2005-12-05

申请人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

发明人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

IPC分类号： G09G5/00 ,  G06T1/00

CPC分类号： G06T15/30

摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation. The clipping engine is configured to perform a set of clipping operations with respect to the canonical representation.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，图形处理装置包括连接到映射单元的映射单元和剪辑引擎。 映射单元被配置为将图形原语映射到规范表示。 剪辑引擎被配置为执行关于规范表示的一组剪切操作。

公开(公告)号：US06507886B1

公开(公告)日：2003-01-14

申请号：US09847914

申请日：2001-05-01

申请人： Andrea Y. J. Chen ,  Lordson L. Yue

发明人： Andrea Y. J. Chen ,  Lordson L. Yue

IPC分类号： G06F1200

CPC分类号： G06F13/1631

摘要： A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests. Similarly, the main memory scheduler prioritizes a majority of read requests ahead of write requests, so that a processor that originates a read request is not normally stalled by a previously issued write request, as would be the case in first-in-first-out (FIFO) issuance of memory requests. The main memory scheduler performs FIFO processing, for example, when a later-received read request and an earlier-received write request both access the same location in main memory, or when the number of pending write requests exceeds a predetermined limit. Such prioritization of requests can be made programmable, depending on signals held in storage elements that are included in the main memory scheduler.