公开(公告)号：US5036528A

公开(公告)日：1991-07-30

申请号：US471915

申请日：1990-01-29

申请人： Duc N. Le ,  Lordson L. Yue ,  Cirillo L. Costantino ,  David P. Chengson ,  Duc N. Le ,  Lordson L. Yue ,  Aurangzeb K. Khan

发明人： Duc N. Le ,  Lordson L. Yue ,  Cirillo L. Costantino ,  David P. Chengson ,  Duc N. Le ,  Lordson L. Yue ,  Aurangzeb K. Khan

IPC分类号： G06F1/12 ,  G06F1/10 ,  H03K5/00

CPC分类号： G06F1/10

摘要： The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

公开(公告)号：US4951050A

公开(公告)日：1990-08-21

申请号：US268422

申请日：1988-11-08

申请人： Aurangzeb K. Khan ,  Lordson L. Yue

发明人： Aurangzeb K. Khan ,  Lordson L. Yue

IPC分类号： H03M5/20

CPC分类号： H03M5/20

摘要： Encoding and decoding circuits, utilizing high speed ECL-like logic, simultaneously transmit and receive multiple binary signals via a single I/O pin.

摘要翻译： 使用高速ECL逻辑的编码和解码电路通过单个I / O引脚同时发送和接收多个二进制信号。

公开(公告)号：US4931672A

公开(公告)日：1990-06-05

申请号：US318435

申请日：1989-03-03

申请人： Aurangzeb K. Khan

发明人： Aurangzeb K. Khan

IPC分类号： H03K19/018 ,  H03K19/082

CPC分类号： H03K19/0826 ,  H03K19/01812

摘要： The present invention provides an integrated circuit that has both driver and receiver functions. The circuit of the present invention has two interrelated parts. The first part of the circuit converts true TTL signals to true ECL signals. The second part of the circuit accepts true ECL signals and drives a tri-state true TTL bus. The novel design of the present invention provides a common circuit that acts as an input reference for the circuit that converts true TTL signals to true ECL signals and as a tri-state clamp for the circuit that accepts true ECL signals and drives a tri-state true TTL bus. Using the same circuit components to perform functions in two separate circuits reduces the component count of the resulting circuit and increases the circuit's power/device count figure of merit.

摘要翻译： 本发明提供了具有驱动器和接收器功能的集成电路。 本发明的电路具有两个相互关联的部分。 电路的第一部分将真正的TTL信号转换为真实的ECL信号。 电路的第二部分接受真实的ECL信号并驱动三态真正的TTL总线。 本发明的新颖设计提供了一种公共电路，其作为用于将真实TTL信号转换为真实ECL信号的电路的输入参考，并且作为用于接受真实ECL信号并驱动三态的电路的三态钳位 真正的TTL总线。 使用相同的电路元件在两个独立的电路中执行功能可以减少所得电路的元件数量，并增加电路的功率/器件数量的品质因数。

公开(公告)号：US5034964A

公开(公告)日：1991-07-23

申请号：US268423

申请日：1988-11-08

申请人： Aurangzeb K. Khan ,  Robert Horst ,  Lordson L. Yue

发明人： Aurangzeb K. Khan ,  Robert Horst ,  Lordson L. Yue

IPC分类号： G05F1/577 ,  G05F3/22 ,  H04L5/02

CPC分类号： H04L5/02 ,  G05F1/577 ,  G05F3/22

摘要： Encoding and decoding circuits are described for functioning as both a time and voltage based transmission system. Multiple binary inputs can be transmitted and received on a single I/O pin by encoder and decoder circuits using high speed emitter coupled-like logic.

摘要翻译： 描述了编码和解码电路，用作基于时间和电压的传输系统。 可以通过编码器和解码器电路在单个I / O引脚上传输和接收多个二进制输入，使用高速发射极耦合式逻辑。

公开(公告)号：US4857776A

公开(公告)日：1989-08-15

申请号：US123093

申请日：1987-11-20

申请人： Aurangzeb K. Khan

发明人： Aurangzeb K. Khan

IPC分类号： H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/082

CPC分类号： H03K19/01812 ,  H03K19/013 ,  H03K19/0826

摘要： The present invention provdes a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels.

公开(公告)号：US4728818A

公开(公告)日：1988-03-01

申请号：US942669

申请日：1986-12-17

申请人： David P. Chengson ,  Aurangzeb K. Khan

发明人： David P. Chengson ,  Aurangzeb K. Khan

IPC分类号： H03K3/286 ,  H03K3/2885 ,  H03K19/086 ,  H03K3/284 ,  H03K3/29

CPC分类号： H03K3/2885 ,  H03K19/0863

摘要： An improved EFL gate which provides concurrent true and complementary outputs. An input transistor has its base coupled to an input and its emitter coupled to an emitter of a reference transistor. The reference transistor has its base coupled to a voltage reference and its collector coupled to the base of a true output transistor. The emitter of the true output transistor provides the true output, while its collector is coupled to a voltage supply. A complementary output transistor has its base coupled to the collector of the input transistor with its emitter providing the complementary output. Its collector is coupled to the voltage supply, as is the collector of the input transistor.

公开(公告)号：US4561095A

公开(公告)日：1985-12-24

申请号：US399670

申请日：1982-07-19

申请人： Aurangzeb K. Khan

发明人： Aurangzeb K. Khan

IPC分类号： G06F11/10 ,  G06F11/267

CPC分类号： G06F11/2215 ,  G06F11/1008 ,  G06F11/1076

摘要： A high speed error correcting random access memory system includes a circuit for generation of a plurality of parity bits from a predetermined combination of data bits of a data word being stored in a random access memory such that these parity bits are stored in memory along with said data bits, and for outputting the data word from said memory system, including correcting for any single bit error in the data word, by a circuit that generates a check word from the data word bits and parity word bits stored in the memory, whose state indicates if any of the data bits are in error, and, if so, proceeds to correct any such erroneous bit. The system also includes a circuit for inserting an erroneous bit of data in memory after the parity bits have been generated, to check operation of the check word generating and output data word correction circuit. The operation of the check word generating circuit can also be suspended so as to enable uncorrected data words to be output by the memory system.

摘要翻译： 高速误差校正随机存取存储器系统包括从存储在随机存取存储器中的数据字的数据位的预定组合产生多个奇偶校验位的电路，使得这些奇偶校验位与所述存储器一起存储在存储器中 数据位，并且用于从所述存储器系统输出数据字，包括通过从存储在存储器中的数据字位和奇偶校验字位产生校验字的电路校正数据字中的任何单个位错误，其状态 指示是否有任何数据位是错误的，如果是，则进行纠正任何这样的错误位。 该系统还包括用于在产生奇偶校验位之后在存储器中插入错误位数据的电路，以检查校验字产生和输出数据字校正电路的操作。 还可以暂停检查字产生电路的操作，以便能够由存储器系统输出未校正的数据字。

公开(公告)号：US4806800A

公开(公告)日：1989-02-21

申请号：US123507

申请日：1987-11-20

申请人： Aurangzeb K. Khan

发明人： Aurangzeb K. Khan

IPC分类号： H03K19/003 ,  H03K19/018 ,  H03K19/092

CPC分类号： H03K19/01812 ,  H03K19/00376

摘要： The present invention provides a high speed low power electrical circuit for converting true TTL level signals to true ECL level signals. The circuit only has a single buffer delay with some small additional delay due to an input emitter follower stage. The circuit includes a clamped, switched emitter follower which acts as a level shifting comparator; a self-centering reference threshold translator; a clamped level shifted input translator; and, an ECL Buffer Driver. The circuit also includes a TTL reference and an ECL reference which are tied together. If the TTL reference level shifts slightly due to temperature changes, supply voltage shifts or other factors, the ECL voltage reference will automatically shift by an appropriate percentage to compensate for the original shift in the TTL reference.

公开(公告)号：US4454939A

公开(公告)日：1984-06-19

申请号：US330933

申请日：1981-12-15

申请人： Richard S. Kampf ,  Chul H. Sohn ,  Aurangzeb K. Khan

发明人： Richard S. Kampf ,  Chul H. Sohn ,  Aurangzeb K. Khan

IPC分类号： G01N35/02 ,  B65G43/00

CPC分类号： G01N35/026

摘要： Apparatus for transporting elongated sample holders in a sample holder storage compartment past an operating station at which sample tubes contained in the sample holders may be removed and then returned to the sample holders. First and second parallel conveyors on opposite sides of the operating station drive the holders toward and away from the operating station. Lateral drive means engage the holders in longitudinal stop positions at opposite ends of the conveyors and drive them laterally between the conveyors to lateral stop positions, one of the holders during lateral movement being driven into and away from an operative position at the operating station. Encoded label means are displayed on each sample holder for indicating the incremental spacing between the sample tubes carried in the sample holder. Detector means are provided for reading the encoded label means and convey a signal in accordance with the label means to control means which control the operation of the first and second conveyor means and of the lateral drive means.

摘要翻译： 用于将样品保持器储存室中的细长样品保持器运送经过样品保持器中包含的样品管的操作站，然后返回到样品保持器的装置。 在操作台的相对侧上的第一和第二平行输送机驱动支架朝向和远离操作台。 横向驱动装置将保持器接合在输送机的相对端处的纵向停止位置，并将它们横向移动到输送机之间到侧向停止位置，其中一个保持件在横向运动期间被驱动进入并远离操作工位的操作位置。 编码的标签装置显示在每个样品架上，用于指示样品架中携带的样品管之间的增量间距。 提供检测器装置用于读取编码的标签装置并根据标签装置传送信号到控制装置，该装置控制第一和第二传送装置和侧向驱动装置的操作。