Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers
    1.
    发明授权
    Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers 有权
    用于制造包括垂直双极结型晶体管和具有间隔物的CMOS晶体管的存储器件的工艺

    公开(公告)号:US08293598B2

    公开(公告)日:2012-10-23

    申请号:US12557396

    申请日:2009-09-10

    IPC分类号: H01L21/8238 H01L27/06

    摘要: A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

    摘要翻译: 在半导体本体中形成用于存储器件的双极选择晶体管和电路MOS晶体管。 双极选择晶体管通过注入掩埋集电器,在掩埋集电极上注入基极区域,在半导体主体上形成硅化物保护掩模,以及注入发射极区域和控制接触区域而形成。 电路MOS晶体管通过在半导体主体上限定栅极形成,在栅极的侧面上形成横向间隔物,并在侧面间隔物的侧面上注入源极和漏极区域。 然后,以自对准的方式在发射极,基极接触,源极和漏极区域以及栅极上形成硅化物区域。 横向间隔物是包括至少两个不同层的多层结构,其中之一用于在双极选择晶体管上形成硅化物保护掩模。 因此,横向间隔件的尺寸与硅化物防护罩的厚度分离。

    PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS
    2.
    发明申请
    PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS 有权
    用于制造包括垂直双极性晶体管的存储器件和具有间隔器的CMOS晶体管的过程

    公开(公告)号:US20100059829A1

    公开(公告)日:2010-03-11

    申请号:US12557396

    申请日:2009-09-10

    IPC分类号: H01L27/06 H01L21/8249

    摘要: A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

    摘要翻译: 在半导体本体中形成用于存储器件的双极选择晶体管和电路MOS晶体管。 双极选择晶体管通过注入掩埋集电器,在掩埋集电极上注入基极区域,在半导体主体上形成硅化物保护掩模,以及注入发射极区域和控制接触区域而形成。 电路MOS晶体管通过在半导体主体上限定栅极形成,在栅极的侧面上形成横向间隔物,并在侧面间隔物的侧面上注入源极和漏极区域。 然后,以自对准的方式在发射极,基极接触,源极和漏极区域以及栅极上形成硅化物区域。 横向间隔物是包括至少两个不同层的多层结构,其中之一用于在双极选择晶体管上形成硅化物保护掩模。 因此,横向间隔件的尺寸与硅化物防护罩的厚度分离。