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    PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS
    2.
    发明申请
    PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS 有权
    用于制造包括垂直双极性晶体管的存储器件和具有间隔器的CMOS晶体管的过程

    公开(公告)号：US20100059829A1

    公开(公告)日：2010-03-11

    申请号：US12557396

    申请日：2009-09-10

    申请人： Fabio Pellizzer ,  Cristina Casellato ,  Michele Magistretti ,  Roberto Colombo ,  Lucilla Brattico

    发明人： Fabio Pellizzer ,  Cristina Casellato ,  Michele Magistretti ,  Roberto Colombo ,  Lucilla Brattico

    IPC分类号： H01L27/06 ,  H01L21/8249

    CPC分类号： H01L27/0623 ,  G11C13/0004 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/2445 ,  H01L29/6656 ,  H01L29/6659 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    摘要： A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

    摘要翻译： 在半导体本体中形成用于存储器件的双极选择晶体管和电路MOS晶体管。 双极选择晶体管通过注入掩埋集电器，在掩埋集电极上注入基极区域，在半导体主体上形成硅化物保护掩模，以及注入发射极区域和控制接触区域而形成。 电路MOS晶体管通过在半导体主体上限定栅极形成，在栅极的侧面上形成横向间隔物，并在侧面间隔物的侧面上注入源极和漏极区域。 然后，以自对准的方式在发射极，基极接触，源极和漏极区域以及栅极上形成硅化物区域。 横向间隔物是包括至少两个不同层的多层结构，其中之一用于在双极选择晶体管上形成硅化物保护掩模。 因此，横向间隔件的尺寸与硅化物防护罩的厚度分离。

    Avoiding degradation of chalcogenide material during definition of multilayer stack structure
    3.
    发明授权
    Avoiding degradation of chalcogenide material during definition of multilayer stack structure 有权
    在多层堆叠结构的定义过程中避免硫族化物材料的退化

    公开(公告)号：US08623697B2

    公开(公告)日：2014-01-07

    申请号：US13132311

    申请日：2008-12-31

    申请人： Michele Magistretti ,  Pietro Petruzza ,  Samuele Sciarrillo ,  Cristina Casellato

    发明人： Michele Magistretti ,  Pietro Petruzza ,  Samuele Sciarrillo ,  Cristina Casellato

    IPC分类号： H01L29/02

    CPC分类号： H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    摘要： A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

    摘要翻译： 公开了一种用于相变存储器（PCM）单元的存储元件结构及其形成方法。 形成存储元件结构的方法包括提供包括硫族化物层（206），金属覆盖层（208）和电介质硬掩模层（210）的多层堆叠，沉积和图案化光致抗蚀剂层（212） 在多层堆叠的顶部，在蚀刻电介质硬掩模层之后，使用光致抗蚀剂层作为蚀刻掩模蚀刻电介质硬掩模层，在蚀刻硫族化物之前去除光致抗蚀剂层，使用电介质硬掩模蚀刻硫族化物层 在所述多层堆叠上沉积间隔电介质（214），并各向异性地蚀刻所述间隔电介质以形成所述多层堆叠的侧壁间隔物（216）。

    Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers
    4.
    发明授权
    Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers 有权
    用于制造包括垂直双极结型晶体管和具有间隔物的CMOS晶体管的存储器件的工艺

    公开(公告)号：US08293598B2

    公开(公告)日：2012-10-23

    申请号：US12557396

    申请日：2009-09-10

    申请人： Fabio Pellizzer ,  Cristina Casellato ,  Michele Magistretti ,  Roberto Colombo ,  Lucilla Brattico

    发明人： Fabio Pellizzer ,  Cristina Casellato ,  Michele Magistretti ,  Roberto Colombo ,  Lucilla Brattico

    IPC分类号： H01L21/8238 ,  H01L27/06

    CPC分类号： H01L27/0623 ,  G11C13/0004 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/2445 ,  H01L29/6656 ,  H01L29/6659 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    摘要： A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

    摘要翻译： 在半导体本体中形成用于存储器件的双极选择晶体管和电路MOS晶体管。 双极选择晶体管通过注入掩埋集电器，在掩埋集电极上注入基极区域，在半导体主体上形成硅化物保护掩模，以及注入发射极区域和控制接触区域而形成。 电路MOS晶体管通过在半导体主体上限定栅极形成，在栅极的侧面上形成横向间隔物，并在侧面间隔物的侧面上注入源极和漏极区域。 然后，以自对准的方式在发射极，基极接触，源极和漏极区域以及栅极上形成硅化物区域。 横向间隔物是包括至少两个不同层的多层结构，其中之一用于在双极选择晶体管上形成硅化物保护掩模。 因此，横向间隔件的尺寸与硅化物防护罩的厚度分离。

    AVOIDING DEGRADATION OF CHALCOGENIDE MATERIAL DURING DEFINITION OF MULTILAYER STACK STRUCTURE
    7.
    发明申请
    AVOIDING DEGRADATION OF CHALCOGENIDE MATERIAL DURING DEFINITION OF MULTILAYER STACK STRUCTURE 有权
    多层堆叠结构定义期间氯化铝材料的避免降解

    公开(公告)号：US20120001145A1

    公开(公告)日：2012-01-05

    申请号：US13132311

    申请日：2008-12-31

    申请人： Michele Magistretti ,  Pietro Petruzza ,  Samuele Sciarrillo ,  Cristina Casellato

    发明人： Michele Magistretti ,  Pietro Petruzza ,  Samuele Sciarrillo ,  Cristina Casellato

    IPC分类号： H01L21/20 ,  H01L45/00 ,  B82Y99/00 ,  B82Y40/00

    CPC分类号： H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    摘要： A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

    摘要翻译： 公开了一种用于相变存储器（PCM）单元的存储元件结构及其形成方法。 形成存储元件结构的方法包括提供包括硫族化物层（206），金属覆盖层（208）和电介质硬掩模层（210）的多层堆叠，沉积和图案化光致抗蚀剂层（212） 在多层堆叠的顶部，在蚀刻电介质硬掩模层之后，使用光致抗蚀剂层作为蚀刻掩模蚀刻电介质硬掩模层，在蚀刻硫族化物之前去除光致抗蚀剂层，使用电介质硬掩模蚀刻硫族化物层 在所述多层堆叠上沉积间隔电介质（214），并各向异性地蚀刻所述间隔电介质以形成所述多层堆叠的侧壁间隔物（216）。