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1.发明授权System for processing VLIW words containing variable length instructions having embedded instruction length identifiers 有权用于处理包含具有嵌入指令长度标识符的可变长度指令的VLIW字的系统公开(公告)号：US07302552B2
公开(公告)日：2007-11-27
申请号：US10963722
申请日：2004-10-14
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30101 , G06F9/3885
摘要： A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.
摘要翻译： 描述了包括独立地并行执行不同数据处理操作的多个数据路径元件的处理器。 提供了被编码的程序指令，以产生用于控制数据路径元件的控制信号。 支持相同数据处理操作的多个指令集，该数据处理操作将由不同指令集的不同指令内的相同数据路径元素进行不同编码。 这可以实现代码压缩，当可以实现很少的并行性并且在可能时指定完全并行性。
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公开(公告)号：US20050257028A1
公开(公告)日：2005-11-17
申请号：US10963722
申请日：2004-10-14
CPC分类号： G06F9/3853 , G06F9/30101 , G06F9/3885
摘要： A processor is described including a plurality of data path elements 2, 4, 6, 8 which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.
摘要翻译： 描述了处理器，其包括独立地并行执行不同数据处理操作的多个数据路径元件2,4,6,8。 提供了被编码的程序指令，以产生用于控制数据路径元件的控制信号。 支持相同数据处理操作的多个指令集，该数据处理操作将由不同指令集的不同指令内的相同数据路径元素进行不同编码。 这可以实现代码压缩，当可以实现很少的并行性并且在可能时指定完全并行性。
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