公开(公告)号：US6133771A

公开(公告)日：2000-10-17

申请号：US263757

申请日：1999-03-05

申请人： Salvatore Portaluri ,  Valerio Pisati ,  Luigi Zangrandi

发明人： Salvatore Portaluri ,  Valerio Pisati ,  Luigi Zangrandi

IPC分类号： H03K7/08 ,  H03K3/17

CPC分类号： H03K7/08

摘要： A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.

摘要翻译： 器件产生具有可编程持续时间的高精度脉冲。 该装置包括第一，第二和第三脉冲发生器电路。 第一脉冲发生器电路在输入端接收脉冲产生指令信号，并在输出端提供用于将寄存器的内容装入计数器的第一脉冲。 第二脉冲发生器电路由第一脉冲发生器电路提供的第一脉冲触发。 第三脉冲发生器电路由第二脉冲发生器电路提供的第二脉冲触发，并产生第三脉冲以重新启动第二脉冲发生器电路。 由第二脉冲发生器电路提供的第二脉冲为计数器形成时钟信号以产生计数器的减量。 来自计数器的输出信号是要产生的脉冲信号。 脉冲信号的持续时间由计数器的内容决定。

公开(公告)号：US06523057B1

公开(公告)日：2003-02-18

申请号：US09307083

申请日：1999-05-07

申请人： Pierandrea Savo ,  Luigi Zangrandi ,  Stefano Marchese

发明人： Pierandrea Savo ,  Luigi Zangrandi ,  Stefano Marchese

IPC分类号： G06F750

CPC分类号： G06F7/5095 ,  G06F2207/3884

摘要： A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a preceding clock period. The accumulator also includes at least one second stage having incrementer/decrementer means for performing an increment, decrement or identity operation on a most significant part of the output of the accumulator. The incrementer/decrementer means includes logic means for triggering the increment, a decrement or identity operation on the most significant part of the accumulator output based on a decision made on results obtained at the previous clock period.

摘要翻译： 高速，宽动态范围的数字累加器包括第一加法器级，其中从前一时钟周期将输入加法相加到累加器的输出的最低有效部分的值。 累加器还包括至少一个第二级，其具有递增器/减法器装置，用于在累加器的输出的最重要部分上执行增量，减量或标识操作。 加法器/递减器装置包括用于基于对在先前时钟周期获得的结果的决定来触发增量的触发增量，累加器输出的最高有效部分的递减或识别操作的逻辑装置。