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公开(公告)号：US12113534B2
公开(公告)日：2024-10-08
申请号：US18193078
申请日：2023-03-30
Applicant: Kwang Hee Kim
Inventor： Kwang Hee Kim
CPC classification number: H03K3/017 , H03K3/313 , H03K3/356034 , H03K7/08
Abstract: Provided are a device for adjusting an ultrasonic resonance frequency and a method of controlling the same. A device according to an embodiment of the present disclosure includes a circuit board configured to determine and output a resonance frequency. In addition, the device includes a frequency adjustor connected to at least one of a plurality of circuits mounted on the circuit board.
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公开(公告)号：US20240333139A1
公开(公告)日：2024-10-03
申请号：US18128972
申请日：2023-03-30
Inventor： Shengyuan LI , Leon Samuel WANG , I-Ning KU , Xicheng JIANG
Abstract: An apparatus includes a circuitry to perform a first startup stage and to vary, during a second startup stage subsequent to the first startup stage, a duty cycle of a pulse controlling one or more switches of the circuitry.
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公开(公告)号：US20240314005A1
公开(公告)日：2024-09-19
申请号：US18592793
申请日：2024-03-01
Applicant: NEC Corporation
Inventor： Masaaki TANIO
CPC classification number: H04L25/4902 , H03K4/026 , H03K7/08
Abstract: A signal modulation apparatus includes: a reference signal generator that generates an analog reference signal by removing at least one harmonic signal component corresponding to at least one higher-order frequency from a triangular wave signal; a modulation signal generator that performs pulse width modulation for comparing the analog reference signal with an analog input signal, thereby to generate an analog modulation signal; a digital signal converter that converts the analog modulation signal to a digital output signal; and a nonlinear converter that performs nonlinear conversion corresponding to waveform conversion for converting the triangular wave signal to the analog reference signal, on the digital output signal or the analog input signal.
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公开(公告)号：US20240213962A1
公开(公告)日：2024-06-27
申请号：US18541152
申请日：2023-12-15
Applicant: Canon Kabushiki Kaisha
Inventor： ICHIRO IIJIMA , HIROTAKA ITTOGI
CPC classification number: H03K3/017 , H03K7/08 , H04L7/0087
Abstract: In a data carrier apparatus, a first determination unit determines a duty ratio of each pulse of a pulse signal received from a data carrier driving apparatus, and a second determination unit determines a frequency of each pulse of the received pulse signal. A calibration unit performs calibration of a reference value to be used for determination performed by the second determination unit, during a calibration period. A demodulation unit demodulates data conveyed by the received pulse signal. The demodulation unit performs first demodulation based on a determination result of the first determination unit during the calibration period, and start second demodulation based on the determination result of the first determination unit and a determination result of the second determination unit when the calibration period ends.
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公开(公告)号：US20240195400A1
公开(公告)日：2024-06-13
申请号：US18454507
申请日：2023-08-23
Inventor： Min-Hyung CHO , Yi-Gyeong KIM , Su-Jin PARK , Young-Deuk JEON
CPC classification number: H03K7/08 , H03K5/05 , H03K5/131 , H03K5/15066
Abstract: Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
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Patent Agency Ranking
公开(公告)号：US11996962B2
公开(公告)日：2024-05-28
申请号：US17768979
申请日：2020-10-16
Applicant: Rohm Co., Ltd.
Inventor： Shinya Masuda , Satoshi Tanaka , Toru Mukai , Hiroki Yamakami
CPC classification number: H04L25/49 , H03K7/08 , H04B14/026 , H04B14/046 , H04L25/03
Abstract: A communication system is configured to use a pulse width modulation signal as transmission code among a plurality of nodes connected to a communication line. A master node includes a transmission transistor connected to the communication line, a detector configured to detect a variation in current during the on-period of the transmission transistor, and a communication circuit configured to determine the off-timing of the transmission transistor based on the timing of occurrence of the variation in current (i.e., the on-timing of a second transmission transistor provided in a slave node). For example, the communication circuit can be configured to determine the off-timing of the transmission transistor such that the simultaneously-on period TB of the transmission transistor and the second transmission transistor fulfills TB=(2n−1)/2f, where f is the frequency of EMI noise.
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公开(公告)号：US20240128859A1
公开(公告)日：2024-04-18
申请号：US18046966
申请日：2022-10-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Huihuang CHEN
CPC classification number: H02M1/4208 , H03K7/08
Abstract: A pulse width modulation (PWM) system includes a PWM circuit and a controller. The PWM circuit includes a counter, a period register, and a duty cycle register. The controller is coupled to the PWM circuit. The controller is configured to calculate a period value and a duty cycle value. The controller is also configured to load the duty cycle value into the duty cycle register responsive to a count value of the counter being equal to a value of the duty cycle register and the duty cycle value being less than the period value.
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公开(公告)号：US20240088876A1
公开(公告)日：2024-03-14
申请号：US18451262
申请日：2023-08-17
Applicant: STMicroelectronics S.r.I.
Inventor： Ivan Floriani , Elena Brigo
IPC: H03K3/037 , H03K5/1534 , H03K7/08 , H03K17/687
CPC classification number: H03K3/0375 , H03K5/1534 , H03K7/08 , H03K17/6871
Abstract: A controller for an electronic circuit that includes a first and a second switch is provided. The controller includes an event detector stage that receives logic electrical signals and a pulse generator circuit, which is coupled to the event detector stage and generates a dead time signal based on edges of the logic electrical signals detected by the event detector stage. The dead time signal includes pulses delimited by an edge of a first type and by a subsequent edge of a second type. A combinatorial sampling circuit generates a first and a second sampled preliminary signal. An update stage updates the values of the first and the second control signals at each pulse of the dead time signal based on the first and the second sampled preliminary signals, subsequently to the edge of the first type or the second type of the pulse of the dead time signal.
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公开(公告)号：US11901948B2
公开(公告)日：2024-02-13
申请号：US17583396
申请日：2022-01-25
Applicant: Carl Zeiss SMT GmbH
Inventor： Cornelius Richt , Mohammad Awad
IPC: H04B10/524 , G02B27/28 , H03K7/08
CPC classification number: H04B10/524 , G02B27/283 , H03K7/08
Abstract: A modulation device includes: a signal splitter configured to generate: i) an M-bit wide partial signal comprising M more significant bits of an N-bit wide input signal; and ii) an L-bit wide partial signal comprising L less significant bits of the N-bit wide input signal, where L=N−M; a first modulation unit configured to generate a 1-bit wide pulse density modulation signal on the basis of the L-bit wide partial signal; a summation unit configured to generate an M-bit wide summation signal on the basis of the M-bit wide partial signal and the 1-bit wide pulse density modulation signal; and a second modulation unit configured to generate a 1-bit wide pulse width modulation signal on the basis of the M-bit wide summation signal.
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公开(公告)号：US11888507B2
公开(公告)日：2024-01-30
申请号：US17408241
申请日：2021-08-20
Applicant: Adesto Technologies Corporation
Inventor： Rishi Singh , Darren Collins , Cormac O'Sullivan
IPC: G06F3/033 , H04B1/16 , H03F1/42 , H03F3/19 , H03F3/45 , H03K3/011 , H03K7/08 , H03M1/12 , H03M1/66 , H04B1/12 , H04B1/18 , H04B7/0426 , H03K5/04
CPC classification number: H04B1/16 , H03F1/42 , H03F3/19 , H03F3/45475 , H03K3/011 , H03K5/04 , H03K7/08 , H03M1/128 , H03M1/1215 , H03M1/662 , H04B1/126 , H04B1/18 , H04B7/043 , H03F2200/294 , H03F2200/36 , H03F2200/451
Abstract: A receiver can include a first set of one or more amplifier stages configured to amplify input signals in a plurality of communication bands. The receiver can further include a second and third set of one or more amplifier stages. The second set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a first one of the plurality of communication bands. Alternatively, the third set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a second one of the plurality of communication bands. A first set of one or more mixers can be configured to receive the input signals in the first communication band amplified by the second set of one or more amplifier stages, to receive one or more local oscillator signals for the first communication band, and to generate a baseband signal from a frequency difference of the signal of the first communication band and the one or more local oscillator signals for the first communication band. A second set of one or more mixers can be configured to receive the input signal in the second communication band amplified by the third set of one or more amplifier stages, to receive one or more local oscillator signals for the second communication band, and to generate a baseband signal of the second communication band.
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