-
1.发明授权Structure for silent invalid state transition handling in an SMP environment 有权在SMP环境中静默无效状态转换处理的结构公开(公告)号：US08195892B2
公开(公告)日：2012-06-05
申请号：US12105970
申请日：2008-04-18
CPC分类号： G06F12/0817 , G06F12/0808
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line.
摘要翻译： 可以提供体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构包括对称多处理（SMP）系统。 该系统包括多个节点。 每个节点包括节点控制器和彼此交叉耦合的多个处理器。 该系统还包括耦合到每个节点控制器的至少一个缓存目录，以及耦合到每个节点控制器的无效状态转换逻辑。 无效状态转移逻辑包括能够识别本地节点中的高速缓存行的无效状态转换的程序代码，以驱逐高速缓存行的相应高速缓存目录条目，并将无效状态转换通知转发给节点控制器 为了使家庭节点驱逐高速缓存行的相应高速缓存目录条目，缓存行的主节点。
-
公开(公告)号：US20080120469A1
公开(公告)日：2008-05-22
申请号：US11562562
申请日：2006-11-22
申请人： Marcus L. Kornegay , Ngan N. Pham
发明人： Marcus L. Kornegay , Ngan N. Pham
IPC分类号： G06F12/08
CPC分类号： G06F12/121 , G06F12/122
摘要： A method for cache management is disclosed. The method can assign or determined identifiers for lines of binary code that are, or will be stored in cache. The method can create a cache directory that utilizes the identifier to keep an eviction count and/or a reload count for cached lines. Thus, each time a line is entered into, or evicted from cache, the cache eviction log can be amended accordingly. When a processor receives or creates an instruction that requests that a line be evicted from cache, a cache manager log can identify a line, or lines of binary code to be evicted based on data by accessing the cache directory and then the line(s) can be evicted.
摘要翻译： 公开了一种用于高速缓存管理的方法。 该方法可以为已经或将要存储在高速缓存中的二进制代码行分配或确定标识符。 该方法可以创建一个缓存目录，利用该标识符来保存缓存行的逐出计数和/或重载计数。 因此，每当一行被输入或从高速缓存中逐出时，可以相应地修改缓存驱逐日志。 当处理器接收或创建请求将行从高速缓存中移出的指令时，高速缓存管理器日志可以通过访问高速缓存目录然后基于数据来标识要被逐出的二进制代码的行或行， 可以驱逐
-
3.发明申请METHOD FOR IDENTIFYING, TRACKING, AND STORING HOT CACHE LINES IN AN SMP ENVIRONMENT 审中-公开在SMP环境中识别，跟踪和存储热缓冲线的方法公开(公告)号：US20080104323A1
公开(公告)日：2008-05-01
申请号：US11553268
申请日：2006-10-26
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F12/0811 , G06F12/0831
摘要： The invention is directed to the identifying, tracking, and storing of hot cache lines in an SMP environment. A method in accordance with an embodiment of the present invention includes: accessing, by a first processor, a cache line from main memory; modifying and storing the cache line in the L2 cache of the first processor; requesting, by a second processor, the cache line; identifying, by the first processor, that the cache line stored in the L2 cache of the first processor has previously been modified; marking, by the first processor, the cache line as a hot cache line; forwarding the hot cache line to the second processor; modifying, by the second processor, the hot cache line; and storing the hot cache line in the hot cache of the second processor.
摘要翻译： 本发明涉及在SMP环境中识别，跟踪和存储热缓存行。 根据本发明的实施例的方法包括：由第一处理器访问来自主存储器的高速缓存行; 将所述高速缓存线修改并存储在所述第一处理器的所述L2高速缓存中; 由第二处理器请求所述高速缓存行; 由第一处理器识别存储在第一处理器的L2高速缓存中的高速缓存行先前已被修改; 由第一处理器将高速缓存行标记为热缓存行; 将热缓存行转发到第二处理器; 由第二处理器修改热缓存行; 以及将所述热缓存行存储在所述第二处理器的热缓存中。
-
公开(公告)号：US20070294484A1
公开(公告)日：2007-12-20
申请号：US11425011
申请日：2006-06-19
IPC分类号： G06F13/28
CPC分类号： G06F12/0817
摘要： Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state transition handling in an SMP environment. In one embodiment of the invention, a cache coherency method can be provided. The cache coherency method can include identifying an invalid state transition for a cache line in a local node, evicting a corresponding cache directory entry for the cache line, forwarding an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line, and relinquishing ownership of the cache line to the home node.
摘要翻译： 本发明的实施例解决了有关高速缓存一致性管理的本领域的缺陷，并提供了一种用于在SMP环境中进行无声无效状态转换处理的新颖且非显而易见的方法，系统和装置。 在本发明的一个实施例中，可以提供高速缓存一致性方法。 缓存一致性方法可以包括识别本地节点中的高速缓存线的无效状态转换，驱逐高速缓存行的相应高速缓存目录条目，将无效状态转换通知转发到用于高速缓存线的家庭节点的节点控制器 家庭节点命令驱逐高速缓存行的相应高速缓存目录条目，并将高速缓存行的所有权放弃到主节点。
-
公开(公告)号：US20100325367A1
公开(公告)日：2010-12-23
申请号：US12487915
申请日：2009-06-19
申请人： Marcus L. Kornegay , Ngan N. Pham
发明人： Marcus L. Kornegay , Ngan N. Pham
CPC分类号： G06F12/0804 , G06F12/0817
摘要： A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is cached in a write-back cache located in a memory controller hardware. The write-back cache holds data being written back to main memory for a period of time prior to writing the data to main memory. If the data is cached in the write-back cache, the data is removed from the write-back cache and forwarded to the requesting processor. The cache coherency state in the coherency directory entry for the data is updated to reflect the current cache coherency state of the data based on the requesting processor's intended use of the data.
摘要翻译： 用于临时保存高速缓存行的回写一致性数据高速缓存。 在接收到数据的处理器请求时，从相干目录确定数据的副本是否被缓存在位于存储器控制器硬件中的写回高速缓存中。 在将数据写入主存储器之前的一段时间内，回写缓存将数据写回到主存储器。 如果数据被缓存在回写缓存中，则数据将从写回缓存中移除并转发到请求处理器。 数据的一致性目录条目中的高速缓存一致性状态被更新以基于请求处理器对数据的预期用途反映数据的当前高速缓存一致性状态。
-
6.发明申请METHOD AND SYSTEM FOR INTELLIGENT AND DYNAMIC CACHE REPLACEMENT MANAGEMENT BASED ON EFFICIENT USE OF CACHE FOR INDIVIDUAL PROCESSOR CORE 失效基于有效使用个人处理器核心的高速缓存的智能和动态缓存更换管理方法与系统公开(公告)号：US20090157970A1
公开(公告)日：2009-06-18
申请号：US11955670
申请日：2007-12-13
申请人： Marcus L. Kornegay , Ngan N. Pham
发明人： Marcus L. Kornegay , Ngan N. Pham
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/121 , G06F2212/1021
摘要： Determining and applying a cache replacement policy for a computer application running in a computer processing system is accomplished by receiving a processor core data request, adding bits on each cache line of a plurality of cache lines to identify a core ID of an at least one processor core that provides each cache line in a shared cache, allocating a tag table for each processor core, where the tag table keeps track of an index of processor core miss rates, and setting a threshold to define a level of cache usefulness, depending on whether or not the index of processor core miss rates exceeds the threshold. Checking the threshold and when the threshold is not exceeded, then a shared cache standard policy for cache replacement is applied. When the threshold is exceeded, then the cache line from the processor core running the application is evicted from the shared cache.
摘要翻译： 确定和应用在计算机处理系统中运行的计算机应用的高速缓存替换策略是通过接收处理器核心数据请求来实现的，该处理器核心数据请求在多个高速缓存行的每条高速缓存线上添加位以识别至少一个处理器的核心ID 核心，它将共享高速缓存中的每条高速缓存行分配给每个处理器核心的标签表，其中标签表跟踪处理器核心未命中率的索引，以及设置阈值以定义缓存的有用性级别，这取决于是否 或者处理器核心错误率的索引不是超过阈值。 检查阈值和何时不超过阈值，然后应用用于高速缓存替换的共享高速缓存标准策略。 当超过阈值时，来自运行应用程序的处理器核心的高速缓存行从共享高速缓存中逐出。
-
公开(公告)号：US20080313427A1
公开(公告)日：2008-12-18
申请号：US12137618
申请日：2008-06-12
CPC分类号： G06F12/0817
摘要： A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.
摘要翻译： 用于在多处理器系统中维护数据一致性的系统包括具有高速缓存和目录的第一处理器，具有目录的第二处理器，以及具有目录并与第一和第二处理器分离的至少一个附加处理器。 第一处理器被配置为确定在第一处理器的高速缓存中是否没有找到数据线，并将数据线的请求转发到第二处理器。 第二处理器被配置为将数据线从第二处理器转发到第一处理器，更新第二处理器的目录以反映被转发到第一处理器的数据线，并将目录更新消息转发到至少一个附加 处理器来反映被转发到第一处理器的数据线。 目录中的条目包括存储器地址，最近的数据保持器和线路状态。
-
公开(公告)号：US20080235452A1
公开(公告)日：2008-09-25
申请号：US12113306
申请日：2008-05-01
申请人： MARCUS L. KORNEGAY , Ngan N. Pham
发明人： MARCUS L. KORNEGAY , Ngan N. Pham
IPC分类号： G06F12/00
CPC分类号： G06F12/121 , G06F12/084 , G06F12/127
摘要： A design structure embodied in a machine readable storage medium for of designing, manufacturing, and/or testing for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores is provided. The design structure includes means for receiving from a processor core a request to load a cache line in the shared cache; means for determining whether the shared cache is full; means for determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and means for evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.
摘要翻译： 提供了一种体现在用于在具有由多个处理器核共享的高速缓存的多核处理环境中的共享高速缓存驱逐的设计，制造和/或测试的机器可读存储介质中的设计结构。 该设计结构包括用于从处理器核心接收在共享高速缓存中加载高速缓存行的请求的装置; 用于确定共享缓存是否已满的装置; 用于确定在所述共享高速缓存中是否存储高速缓存行的装置，如果所述共享高速缓存已满，则所述共享高速缓存已被所述共享高速缓存的所有处理器核心所访问的高速缓存行存储; 以及如果高速缓存行存储在已被共享高速缓存的少于所有处理器核心的共享缓存中存储的共享高速缓存中，则驱逐已经被少于所有共享高速缓存的处理器核心访问的高速缓存行的装置。
-
公开(公告)号：US20080209131A1
公开(公告)日：2008-08-28
申请号：US12112910
申请日：2008-04-30
申请人： Marcus L. Kornegay , Ngan N. Pham
发明人： Marcus L. Kornegay , Ngan N. Pham
IPC分类号： G06F12/08
CPC分类号： G06F12/121 , G06F12/122 , G06F12/127
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processing system. The process system generally includes a processor, cache coupled to the processor to provide at least one line of binary storage to the processor module, an eviction management module coupled to the processor to monitor lines of code interacting with the cache and to count storage related occurrences of the lines of code with respect to the cache, the lines of code having an identifier, and a cache directory to store the count and the identifier, wherein if processor requests cache capacity, the cache directory provides eviction related data for a line of code stored in the cache to the processor.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构通常包括处理系统。 处理系统通常包括处理器，缓存器，耦合到处理器，以向处理器模块提供至少一行二进制存储器;驱逐管理模块，耦合到处理器，以监视与高速缓存相互作用的代码行，并计数存储相关事件 代码行相对于高速缓存，代码行具有标识符和高速缓存目录以存储计数和标识符，其中如果处理器请求高速缓存容量，则高速缓存目录提供一行代码的驱逐相关数据 存储在缓存中到处理器。
-
10.发明授权Dynamic initial cache line coherency state assignment in multi-processor systems 有权多处理器系统中动态初始缓存行一致性状态分配公开(公告)号：US08838909B2
公开(公告)日：2014-09-16
申请号：US11775085
申请日：2007-07-09
CPC分类号： G06F12/0815
摘要： A method, system, and computer program product for providing lines of data from shared resources to caching agents are provided. The method, system, and computer program product provide for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.
摘要翻译： 提供了一种用于从共享资源到高速缓存代理提供数据行的方法，系统和计算机程序产品。 方法，系统和计算机程序产品提供用于从存储在共享资源中的数据行接收来自缓存代理的请求，将多个相关性状态中的一个作为数据行的初始一致性状态分配， 所述多个相关性状态可被分配为所述数据行的初始相关性状态，并且以分配给所述数据线的初始相关性状态向所述缓存代理提供所述数据行。
-
-
-
-
-
-
-
-
-
搜索结果
28 条记录 (耗时 0.014 秒)
