公开(公告)号：US11921633B2

公开(公告)日：2024-03-05

申请号：US17728468

申请日：2022-04-25

申请人： PURE STORAGE, INC.

发明人： Ethan L. Miller ,  Ronald Karr

IPC分类号： G06F12/08 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/122 ,  G06F12/128

CPC分类号： G06F12/0802 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/0685 ,  G06F12/122 ,  G06F12/128 ,  G06F3/0656 ,  G06F2212/1044

摘要： Deduplicating data based on recently reading the data, including: determining whether a calculated signature for write data matches a particular signature corresponding to data that was recently read from the storage device, wherein the signature is calculated using the write data as input; and after determining that the calculated signature for the write data matches the particular signature, obtaining the data that was recently read and comparing the data that was recently read to the write data.

公开(公告)号：US11768777B2

公开(公告)日：2023-09-26

申请号：US16749175

申请日：2020-01-22

申请人： EMC IP Holding Company LLC

发明人： Jai P. Gahlot ,  Shiv S. Kumar

IPC分类号： G06F12/122 ,  G06F12/14 ,  G06F16/2455

CPC分类号： G06F12/122 ,  G06F12/1416 ,  G06F12/1483 ,  G06F16/24552 ,  G06F2212/604

摘要： Methods, apparatus, and processor-readable storage media for application aware cache management are provided herein. An example computer-implemented method includes maintaining a data structure comprising at least one entry indicative of an importance of at least one of a plurality of applications associated with a storage system; and controlling whether or not a particular data item requested by one of the plurality of applications is cached in a cache memory of the storage system based at least in part on the at least one entry of the data structure.

公开(公告)号：US11663168B2

公开(公告)日：2023-05-30

申请号：US17195596

申请日：2021-03-08

申请人： Box, Inc.

发明人： Ritik Malhotra ,  Tanooj Luthra ,  Sri Sarat Ravikumar Tallamraju

IPC分类号： G06F16/20 ,  G06F16/182 ,  G06F9/46 ,  G06F16/23 ,  G06F16/172 ,  G06F16/185 ,  G06F16/188 ,  G06F16/17 ,  G06F16/174 ,  G06F16/176 ,  G06F16/957 ,  H04L67/00 ,  G06F12/1081 ,  H04L65/70 ,  H04L65/75 ,  H04L9/40 ,  H04L67/1097 ,  G06F12/0891 ,  G06F12/122 ,  H04L67/06 ,  H04N19/40 ,  H04L65/80 ,  G06F16/242 ,  G06F16/22 ,  G06F16/11

CPC分类号： G06F16/182 ,  G06F9/46 ,  G06F12/0891 ,  G06F12/1081 ,  G06F12/122 ,  G06F16/113 ,  G06F16/172 ,  G06F16/1727 ,  G06F16/1748 ,  G06F16/1774 ,  G06F16/183 ,  G06F16/185 ,  G06F16/188 ,  G06F16/196 ,  G06F16/22 ,  G06F16/23 ,  G06F16/2443 ,  G06F16/9574 ,  H04L63/0428 ,  H04L65/70 ,  H04L65/762 ,  H04L65/80 ,  H04L67/06 ,  H04L67/1097 ,  H04L67/34 ,  H04N19/40 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/154 ,  G06F2212/463 ,  G06F2212/60 ,  G06F2212/657

摘要： A server in a cloud-based environment interfaces with storage devices that store shared content accessible by two or more users. Individual items within the shared content are associated with respective object metadata that is also stored in the cloud-based environment. Download requests initiate downloads of instances of a virtual file system module to two or more user devices associated with two or more users. The downloaded virtual file system modules capture local metadata that pertains to local object operations directed by the users over the shared content. Changed object metadata attributes are delivered to the server and to other user devices that are accessing the shared content. Peer-to-peer connections can be established between the two or more user devices. Object can be divided into smaller portions such that processing the individual smaller portions of a larger object reduces the likelihood of a conflict between user operations over the shared content.

公开(公告)号：US20180349306A1

公开(公告)日：2018-12-06

申请号：US15826138

申请日：2017-11-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： FLORIAN A. AUERNHAMMER ,  DANIEL WIND

IPC分类号： G06F13/24 ,  G06F12/122

CPC分类号： G06F13/24 ,  G06F9/4812 ,  G06F9/542 ,  G06F12/122 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2213/2424

摘要： A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

公开(公告)号：US20180314646A1

公开(公告)日：2018-11-01

申请号：US16028265

申请日：2018-07-05

申请人： Huawei Technologies Co., Ltd.

发明人： Jun Xu ,  Yongbing Huang ,  Yuangang Wang

IPC分类号： G06F12/121 ,  G06F12/0871 ,  G06F12/0804

CPC分类号： G06F12/121 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0871 ,  G06F12/122 ,  G06F2212/1021

摘要： A cache management method, a cache controller, and a computer system are provided. In the method, the cache controller obtains an operation instruction; when a destination address in the operation instruction hits no cache line cache line in a cache of the computer system, and the cache includes no idle cache line, the cache controller selects a to-be-replaced cache line from a replacement set, where the replacement set includes at least two cache lines; and the cache controller eliminates the to-be-replaced cache line from the cache, and stores, in the cache, a cache line obtained from the destination address. According to the cache management method, system overheads of cache line replacement can be reduced, and cache line replacement efficiency can be improved.

公开(公告)号：US10078595B2

公开(公告)日：2018-09-18

申请号：US15822189

申请日：2017-11-26

申请人： International Business Machines Corporation

发明人： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC分类号： G06F12/0895 ,  G06F12/123 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC分类号： G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F11/1076 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/262 ,  G06F2212/286 ,  G06F2212/312 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621

摘要： A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.

公开(公告)号：US20180165221A1

公开(公告)日：2018-06-14

申请号：US15374788

申请日：2016-12-09

申请人： Advanced Micro Devices, Inc.

发明人： Mark Fowler

IPC分类号： G06F12/128 ,  G06F12/122

CPC分类号： G06F12/128 ,  G06F12/0888 ,  G06F12/122 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/455 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

摘要： A system and method for efficiently performing data allocation in a cache memory are described. A lookup is performed in a cache responsive to detecting an access request. If the targeted data is found in the cache and the targeted data is of a no allocate data type indicating the targeted data is not expected to be reused, then the targeted data is read from the cache without updating cache replacement policy information for the targeted data responsive to the access. If the lookup results in a miss, to the targeted data is prevented from being allocated in the cache.

公开(公告)号：US20180157594A1

公开(公告)日：2018-06-07

申请号：US15884155

申请日：2018-01-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin J. Ash ,  Matthew G. Borlick ,  Lokesh M. Gupta ,  Matthew J. Kalos

IPC分类号： G06F12/0893 ,  G06F12/0891

CPC分类号： G06F12/0893 ,  G06F12/0802 ,  G06F12/0866 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F17/30132 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/60

摘要： Provided are a computer program product, system, and method for using cache lists for processors to determine tracks in a storage to demote from a cache. Tracks in the storage stored in the cache are indicated in lists. There is one list for each of a plurality of processors. Each of the processors processes the list for that processor to process the tracks in the cache indicated on the list. There is a timestamp for each of the tracks indicated in the lists indicating a time at which the track was added to the cache. Tracks indicated in each of the lists having timestamps that fall within a range of timestamps are demoted

公开(公告)号：US09940253B2

公开(公告)日：2018-04-10

申请号：US14939838

申请日：2015-11-12

申请人： International Business Machines Corporation

发明人： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC分类号： G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC分类号： G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

摘要： A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

公开(公告)号：US09940252B2

公开(公告)日：2018-04-10

申请号：US14939762

申请日：2015-11-12

申请人： International Business Machines Corporation

发明人： Brian E. Bakke ,  Joseph R. Edwards ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Daniel F. Moertl ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth

IPC分类号： G06F12/0895 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

CPC分类号： G06F12/0895 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0806 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/128 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621 ,  G06F2212/69

摘要： A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.