公开(公告)号：US3686639A

公开(公告)日：1972-08-22

申请号：US3686639D

申请日：1969-12-11

申请人： MODICON CORP

发明人： FLETCHER WILLIAM E ,  ROSSEAU LEON B

IPC分类号： G05B15/02 ,  G05B19/05 ,  G06F3/02 ,  G06F19/00

CPC分类号： G05B19/056 ,  G05B2219/13004 ,  G05B2219/13039 ,  G05B2219/13128 ,  G05B2219/13171 ,  G05B2219/13186 ,  G05B2219/14084 ,  G05B2219/15018 ,  G05B2219/15049 ,  Y02P90/86 ,  Y10S715/965

摘要： A small general purpose digital computer is utilized as the basic element of an industrial controller. The digital computer is provided with an executive program comprising function simulating modules. Relay logic, timer and counter simulating modules are disclosed. The modules provide an iterative format for a control circuit to be simulated the format comprising a large number of identical parallel circuit lines each controlling a numbered relay. Each circuit may have a specified number of basic electrical elements connected in series with its relay. The types of electrical elements disclosed are a normally open switch, a normally closed switch, a branch function, and a wire connection or no function. The condition of any particular one of the first three types of electrical elements is controlled by a specified one of the number of relays. A control program comprises a particular choice of electrical elements entered in the circuit lines of the ladder diagram to correspond to an actual circuit diagram of a desired control circuit. The system is provided with a simple detachable programming panel or console with which an ordinary industrial engineer having no computer programming experience can program his control program by positioning each required basic electrical element in the format provided and specifying the relay of another circuit line controlling the condition of the elements. He enters the set time for each relay which is to be timer controlled. An internal clock is provided for the timing function. He also enters the total count and the simulated relay whose cycles are to be counted for each relay which is to be counter controlled. A plurality of the numbered relays may each be conditioned only by an external device connected to an identically numbered input terminal. Another plurality of the numbered relays each control the signal supplied to an identically numbered output terminal which may be connected to external devices. In use, the executive program continuously and repeatedly runs through the ladder diagram control circuit line by line, updating the condition of each electrical element in accordance with the referenced numbered relay; updating the condition of each numbered relay in accordance with the condition of the electrical elements or input terminal in circuit therewith; and updating the condition of each output terminal in accordance with its associated numbered relay. Provision is made for communicating with the computer controller via ordinary telephone lines from a central station. The original computer controller is delivered to a customer with the executive program in memory. The control program is added by the customer through the detachable programming console. Both the executive and customer chosen control program can then be read out to the central station and printed or recorded on punched tape for full documentAtion thereof. Further units can be supplied to the customer preprogrammed through use of the punched paper tape. The central station also can communicate with a remote computer controller by means of a central programming console and has the ability to diagnose breakdowns of the computer controller and readin to or readout from any memory location in the remote computer controller.

摘要翻译： 一台小型通用数字计算机被用作t

公开(公告)号：US3740722A

公开(公告)日：1973-06-19

申请号：US3740722D

申请日：1970-07-02

申请人： MODICON CORP

发明人： GREENBERG M ,  FLETCHER W ,  MORLEY R

IPC分类号： G06F9/48 ,  G06F3/00 ,  G06F13/06

CPC分类号： G06F9/4812 ,  G06F9/4843

摘要： Hardware registers which are addressed in the same manner as the main core memory and exchange data with external devices. The computer has no dedicated registers used as the accumulator, program counter and program counter save. Rather, addressed registers in the main core memory are used for these functions. Preferably, there are a plurality of each group comprising a dedicated computational machine. The computational machine which is being operated is specified by a dedicated machine pointer register. Mass memory, additional computers, as well as input and output devices may be connected to the addressed hardware registers to provide unlimited system expansion. Program instructions may be placed in an addressed hardware register in response to external events. The main core memory provided contains all possible addresses in the ten bit address word of the computer. When an addressed hardware register is connected to the computer, it becomes responsive to the central processing unit, rather than the identically addressed core position. The core position is reactivated when the hardware register is disabled by events either external or internal to the computer. This dual addressing scheme is controlled by two priority levels. All address registers and all dedicated machine registers are connected in parallel to a half duplex transfer bus which provides for transfers between any registers connected thereto under control of a central processing unit. All cycles of the computer are identical and comprise three timing states.

公开(公告)号：US3919507A

公开(公告)日：1975-11-11

申请号：US46331574

申请日：1974-04-23

申请人： MODICON CORP

发明人： MIDDLETON JR CHARLES F

IPC分类号： H01H9/20

CPC分类号： H01H9/20

摘要： A power-protect interlock system which assures interconnection of two units only when the power is off, prevents unwanted disconnection, and prevents unwanted operation of the units is provided by a control knob which operates a movable latch and allows a power switch to be activated only when the units have been interconnected. In the preferred embodiment, one unit incorporates a pin-receiving assembly, and the second unit, which incorporates the control knob, incorporates a pin connection assembly. Also, in the preferred embodiment, the first unit comprises a pivot plate along the top thereof and the second unit incorporates a hook member positioned for engagement with the pivot plate to support the weight of the second unit and allow easy interconnection of the units. Furthermore, the two units incorporate cooperating alignment members to assure precise accurate pin interconnection.

摘要翻译： 一个电源保护互锁系统，仅在电源关闭时确保两个单元的互连，防止不必要的断开，并防止单元的不必要的操作由操作可移动闩锁的控制旋钮提供，并允许仅开启电源开关 当单位互连时。 在优选实施例中，一个单元包括销接收组件，并且包括控制旋钮的第二单元包括销连接组件。 此外，在优选实施例中，第一单元包括沿其顶部的枢转板，并且第二单元包括定位成与枢转板接合以支撑第二单元的重量的钩构件，并且允许单元容易地互连。 此外，两个单元包括协作对准构件以确保精确的针脚互连。

公开(公告)号：US3761893A

公开(公告)日：1973-09-25

申请号：US3761893D

申请日：1970-07-02

申请人： MODICON CORP

发明人： MORLEY R

IPC分类号： G06F9/30 ,  G06F9/48 ,  G06F3/00

CPC分类号： G06F9/4812 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/4843

摘要： Hardware registers which are addressed in the same manner as the main core memory and exchange data with external devices. The computer has no dedicated registers used as the accumulator, program counter and program counter save. Rather, addressed registers in the main core memory are used for these functions. Preferably, there are a plurality of each group comprising a dedicated computational machine. The computational machine which is being operated is specified by a dedicated machine pointer register. Mass memory, additional computers, as well as input and output devices may be connected to the addressed hardware registers to provide unlimited system expansion. Program instructions may be placed in an addressed hardware register in response to external events. The main core memory provided contains all possible addresses in the ten bit address word of the computer. When an addressed hardware register is connected to the computer, it becomes responsive to the central processing unit, rather than the identically addressed core position. The core position is reactivated when the hardware register is disabled by events either external or internal to the computer. This dual addressing scheme is controlled by two priority levels. All address registers and all dedicated machine registers are connected in parallel to a half duplex transfer bus which provides for transfers between any registers connected thereto under control of a central processing unit. All cycles of the computer are identical and comprise three timing states.

摘要翻译： 硬件寄存器以与主核心存储器相同的方式进行寻址，并与外部设备交换数据。 计算机没有用作累加器的专用寄存器，程序计数器和程序计数器保存。 相反，主核心内存中的寻址寄存器用于这些功能。 优选地，存在多个包括专用计算机的每个组。 正在操作的计算机由专用机器指针寄存器指定。