公开(公告)号：US07210056B2

公开(公告)日：2007-04-24

申请号：US10863374

申请日：2004-06-08

Applicant: Magne Sandven ,  Brian Manula ,  Morten Schanke

Inventor： Magne Sandven ,  Brian Manula ,  Morten Schanke

IPC: G06F1/10 ,  G06F5/06

CPC classification number: H04J3/0608

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract translation: 可以提供Infiniband设备。 该设备可以包括具有串行器/解串器的输入端口。 串行器/解串器可以包括：数据缓冲器，用于存储来自接收到的串行数据流的数据并且用于并行地输出所存储的数据;以及代码检测器，用于检测串行数据流中的预定代码模式，并产生代码检测输出 回应。 串行器/解串器还可以包括用于检测串行数据流中的转换并从其重建串行数据时钟的转换检测器，并且用于从串行数据时钟生成多个并行数据时钟，每个并行数据时钟具有不同的相位。 数据缓冲器可以响应于代码检测输出来调整串行数据流内的并行数据组起始位置，并且使得对具有对应于调整的并行数据组开始位置的相位的降频时钟中的一个进行选择。

公开(公告)号：US20070112995A1

公开(公告)日：2007-05-17

申请号：US11280152

申请日：2005-11-16

Applicant: Brian Manula ,  Magne Sandven ,  Ali Bozkaya

Inventor： Brian Manula ,  Magne Sandven ,  Ali Bozkaya

IPC: G06F13/36

CPC classification number: G06F13/423

Abstract: An interconnect apparatus provides for the buffering of information in respective transaction buffers according to transaction type. An additional buffer is dynamically assignable to one of the transaction buffers where additional capacity is required by that transaction buffer.

Abstract translation: 互连装置根据交易类型提供在各个事务缓冲器中缓存信息。 一个额外的缓冲区可以动态分配给事务缓冲区之一，该事务缓冲区需要额外的容量。

公开(公告)号：US07170512B2

公开(公告)日：2007-01-30

申请号：US10133971

申请日：2002-04-26

Applicant: Trefor Southwell ,  Magne Sandven

Inventor： Trefor Southwell ,  Magne Sandven

IPC: G06T17/00

CPC classification number: G06T15/005

Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.

Abstract translation: 一种具有索引处理单元的图形处理器，用于预处理构成三维图像的顶点列表。 预处理方法包括以下步骤。 首先，将三维图像分解为由一组顶点定义的多个基元，每个顶点包含存储在顶点存储区域中并且可由顶点索引寻址的顶点信息。 然后接收所述顶点索引并创建一组唯一索引，其识别一批顶点，并仅将与所述唯一索引对应的顶点加载到顶点存储区域中。 最后使用独特的索引从顶点存储区域中寻址的变换顶点信息创建变换的原始元素。

公开(公告)号：US20070112996A1

公开(公告)日：2007-05-17

申请号：US11280154

申请日：2005-11-16

Applicant: Brian Manula ,  Magne Sandven ,  Marius Gimle

Inventor： Brian Manula ,  Magne Sandven ,  Marius Gimle

IPC: G06F13/36

CPC classification number: G06F13/423

Abstract: An interconnect apparatus provides for the buffering of information among a plurality of retry buffers in an output port. An additional buffer is dynamically assignable to one of the N retry buffer means where additional capacity is required by that retry buffer.

Abstract translation: 互连装置提供在输出端口中的多个重试缓冲器之间缓冲信息。 一个附加的缓冲区可动态地分配给N个重试缓冲器装置之一，该重试缓冲器需要额外的容量。

公开(公告)号：US20070112994A1

公开(公告)日：2007-05-17

申请号：US11280148

申请日：2005-11-16

Applicant: Magne Sandven ,  Morten Schanke ,  Brian Manula

Inventor： Magne Sandven ,  Morten Schanke ,  Brian Manula

IPC: G06F13/36

CPC classification number: G06F13/4059

Abstract: An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequence to a destination. The control logic can further be operable on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet.

Abstract translation: 互连设备包括事务包缓冲器和控制逻辑。 控制逻辑可以顺序地可操作地写入事务分组以便传输到事务分组缓冲器并且将缓冲的事务分组顺序发送到目的地。 控制逻辑还可以在接收到表示未被接收的发送的交易分组的目的地的控制分组的情况下重新发送未接收的交易分组以及在未接收到的交易之后从交易分组缓冲器发送的交易分组 包。

公开(公告)号：US20050273641A1

公开(公告)日：2005-12-08

申请号：US10863374

申请日：2004-06-08

Applicant: Magne Sandven ,  Brian Manula ,  Morten Schanke

Inventor： Magne Sandven ,  Brian Manula ,  Morten Schanke

IPC: G06F13/42 ,  H04J3/06 ,  G06F1/12

CPC classification number: H04J3/0608

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract translation: 可以提供Infiniband设备。 该设备可以包括具有串行器/解串器的输入端口。 串行器/解串器可以包括：数据缓冲器，用于存储来自接收到的串行数据流的数据并且用于并行地输出所存储的数据;以及代码检测器，用于检测串行数据流中的预定代码模式，并产生代码检测输出 回应。 串行器/解串器还可以包括用于检测串行数据流中的转换并从其重建串行数据时钟的转换检测器，并且用于从串行数据时钟生成多个并行数据时钟，每个并行数据时钟具有不同的相位。 数据缓冲器可以响应于代码检测输出来调整串行数据流内的并行数据组起始位置，并且使得对具有对应于调整的并行数据组开始位置的相位的降频时钟中的一个进行选择。