Adaptive clock enable for memory control
    1.
    发明申请
    Adaptive clock enable for memory control 审中-公开
    自适应时钟使能用于存储器控制

    公开(公告)号:US20100169700A1

    公开(公告)日:2010-07-01

    申请号:US12317869

    申请日:2008-12-29

    CPC classification number: G06F1/3275 G06F1/3225 G11C8/18 Y02D10/14

    Abstract: In some embodiments a memory rank idle counter enables de-assertion of a clock enable signal of a rank of a memory for idle systems. Clock enable signal assertion is maintained when there is a lot of traffic to the memory rank. A memory rank idle time prediction counter transfers a value to the memory rank idle counter when the memory rank is idle. Other embodiments are described and claimed.

    Abstract translation: 在一些实施例中,存储器级空闲计数器使得能够取消对空闲系统的存储器的等级的时钟使能信号。 当存储器级别有大量流量时,保持时钟使能信号断言。 当存储器级空闲时,存储器级空闲时间预测计数器将值传送到存储器级空闲计数器。 描述和要求保护其他实施例。

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