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公开(公告)号:US20100169700A1
公开(公告)日:2010-07-01
申请号:US12317869
申请日:2008-12-29
Applicant: Philip Abraham , Steve Kulick , Mahadev Nemani
Inventor: Philip Abraham , Steve Kulick , Mahadev Nemani
IPC: G06F1/04
CPC classification number: G06F1/3275 , G06F1/3225 , G11C8/18 , Y02D10/14
Abstract: In some embodiments a memory rank idle counter enables de-assertion of a clock enable signal of a rank of a memory for idle systems. Clock enable signal assertion is maintained when there is a lot of traffic to the memory rank. A memory rank idle time prediction counter transfers a value to the memory rank idle counter when the memory rank is idle. Other embodiments are described and claimed.
Abstract translation: 在一些实施例中,存储器级空闲计数器使得能够取消对空闲系统的存储器的等级的时钟使能信号。 当存储器级别有大量流量时,保持时钟使能信号断言。 当存储器级空闲时,存储器级空闲时间预测计数器将值传送到存储器级空闲计数器。 描述和要求保护其他实施例。
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公开(公告)号:US20090248945A1
公开(公告)日:2009-10-01
申请号:US12059158
申请日:2008-03-31
Applicant: Navindra Navaratnam , Edward Burton , Mahadev Nemani , Yanmei Tian , Harry Muljono
Inventor: Navindra Navaratnam , Edward Burton , Mahadev Nemani , Yanmei Tian , Harry Muljono
CPC classification number: G06F13/4077 , H04L25/0272
Abstract: In some embodiments, a circuit is provided with a transmitter to generate switching noise during clock events when no transition occurs to reduce data dependent switching noise.
Abstract translation: 在一些实施例中,电路设置有发射机,以便在不发生跳变的时钟事件期间产生开关噪声,以减少依赖于数据的开关噪声。
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