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公开(公告)号：US09285826B2
公开(公告)日：2016-03-15
申请号：US13995274
申请日：2011-12-22
摘要： Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.
摘要翻译： 时钟穿越的技术和装置。 第一管芯上的复位电路产生与标识单个边沿的参考时钟同步的转发的FIFO复位信号。 第一裸片上的时钟产生电路产生参考时钟信号。 第一裸片上的控制电路产生一个转发信号，与转发的时钟同步，该转发的时钟标识一个转发的时钟边沿，与转发的时钟沿固定的定时关系，发送PLL锁定到单个参考边缘。 第二管芯上的锁相环（PLL）被耦合以接收参考时钟信号，PLL产生本地时钟信号。 循环FIFO具有由转发时钟提前的写指针和由本地时钟提前的读指针。
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2.发明申请Method, apparatus and system to generate an interrupt by monitoring an external interface 有权通过监视外部接口产生中断的方法，装置和系统公开(公告)号：US20060143351A1
公开(公告)日：2006-06-29
申请号：US11025381
申请日：2004-12-28
申请人： David Lee , Steve Kulick , Sivakumar Radhakrishnan
发明人： David Lee , Steve Kulick , Sivakumar Radhakrishnan
IPC分类号： G06F13/24
摘要： In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.
摘要翻译： 在一些实施例中，呈现通过监视外部接口来产生中断的方法，装置和系统。 在这方面，引入一个中断代理程序通过串行接口与输入/输出（I / O）扩展器进行通信，并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。
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公开(公告)号：US20140040652A1
公开(公告)日：2014-02-06
申请号：US13995109
申请日：2011-12-22
申请人： Stanley Steve Kulick
发明人： Stanley Steve Kulick
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/24 , G11C7/20 , G11C7/222 , G11C11/40615
摘要： Initialization in multiple clock domains. A first die having a master initialization component generates initialization commands. A local initialization agent on the first die is coupled to receive the initialization commands. The local initialization agent manages initialization of one or more components on the first die. A remote initialization agent on a second die is coupled to receive the initialization commands. The remote initialization agent manages initialization of one or more components on the second die. The master initialization component receives acknowledgement messages from the local initialization agent and the remote initialization agent to manage conflicts and dependencies between the local initialization agent and the remote initialization agent and synchronizes events in multiple clock domains that share a reference clock signal by signaling in the reference clock domain.
摘要翻译： 在多个时钟域中进行初始化。 具有主初始化组件的第一管芯生成初始化命令。 第一裸片上的本地初始化代理被耦合以接收初始化命令。 本地初始化代理管理第一裸片上的一个或多个组件的初始化。 耦合第二裸片上的远程初始化代理以接收初始化命令。 远程初始化代理管理第二管芯上的一个或多个部件的初始化。 主初始化组件从本地初始化代理和远程初始化代理接收确认消息，以管理本地初始化代理和远程初始化代理之间的冲突和依赖关系，并通过参考中的信令来共享参考时钟信号的多个时钟域中的事件 时钟域。
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4.发明授权Method, apparatus and system to generate an interrupt by monitoring an external interface 有权通过监视外部接口产生中断的方法，装置和系统公开(公告)号：US07386640B2
公开(公告)日：2008-06-10
申请号：US11025381
申请日：2004-12-28
IPC分类号： G06F3/00
摘要： In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.
摘要翻译： 在一些实施例中，呈现通过监视外部接口来产生中断的方法，装置和系统。 在这方面，引入一个中断代理程序通过串行接口与输入/输出（I / O）扩展器进行通信，并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。
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公开(公告)号：US20130326205A1
公开(公告)日：2013-12-05
申请号：US13995274
申请日：2011-12-22
摘要： Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.
摘要翻译： 时钟穿越的技术和装置。 第一管芯上的复位电路产生与标识单个边沿的参考时钟同步的转发的FIFO复位信号。 第一裸片上的时钟产生电路产生参考时钟信号。 第一裸片上的控制电路产生一个转发信号，与转发的时钟同步，该转发的时钟标识一个转发的时钟边沿，与转发的时钟沿固定的定时关系，发送PLL锁定到单个参考边缘。 第二管芯上的锁相环（PLL）被耦合以接收参考时钟信号，PLL产生本地时钟信号。 循环FIFO具有由转发时钟提前的写指针和由本地时钟提前的读指针。
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公开(公告)号：US20100169700A1
公开(公告)日：2010-07-01
申请号：US12317869
申请日：2008-12-29
申请人： Philip Abraham , Steve Kulick , Mahadev Nemani
发明人： Philip Abraham , Steve Kulick , Mahadev Nemani
IPC分类号： G06F1/04
CPC分类号： G06F1/3275 , G06F1/3225 , G11C8/18 , Y02D10/14
摘要： In some embodiments a memory rank idle counter enables de-assertion of a clock enable signal of a rank of a memory for idle systems. Clock enable signal assertion is maintained when there is a lot of traffic to the memory rank. A memory rank idle time prediction counter transfers a value to the memory rank idle counter when the memory rank is idle. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，存储器级空闲计数器使得能够取消对空闲系统的存储器的等级的时钟使能信号。 当存储器级别有大量流量时，保持时钟使能信号断言。 当存储器级空闲时，存储器级空闲时间预测计数器将值传送到存储器级空闲计数器。 描述和要求保护其他实施例。
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公开(公告)号：US09274544B2
公开(公告)日：2016-03-01
申请号：US13995109
申请日：2011-12-22
申请人： Stanley Steve Kulick
发明人： Stanley Steve Kulick
IPC分类号： G06F1/12 , G11C7/20 , G06F1/24 , G11C7/22 , G11C11/406
CPC分类号： G06F1/12 , G06F1/24 , G11C7/20 , G11C7/222 , G11C11/40615
摘要： Initialization in multiple clock domains. A first die having a master initialization component generates initialization commands. A local initialization agent on the first die is coupled to receive the initialization commands. The local initialization agent manages initialization of one or more components on the first die. A remote initialization agent on a second die is coupled to receive the initialization commands. The remote initialization agent manages initialization of one or more components on the second die. The master initialization component receives acknowledgement messages from the local initialization agent and the remote initialization agent to manage conflicts and dependencies between the local initialization agent and the remote initialization agent and synchronizes events in multiple clock domains that share a reference clock signal by signaling in the reference clock domain.
摘要翻译： 在多个时钟域中进行初始化。 具有主初始化组件的第一管芯生成初始化命令。 第一裸片上的本地初始化代理被耦合以接收初始化命令。 本地初始化代理管理第一裸片上的一个或多个组件的初始化。 耦合第二裸片上的远程初始化代理以接收初始化命令。 远程初始化代理管理第二管芯上的一个或多个部件的初始化。 主初始化组件从本地初始化代理和远程初始化代理接收确认消息，以管理本地初始化代理和远程初始化代理之间的冲突和依赖关系，并通过参考中的信令来共享参考时钟信号的多个时钟域中的事件 时钟域。
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8.发明申请Bridging Circuitry Between A Memory Controller And Request Agents In A System Having Multiple System Memory Protection Schemes 有权具有多个系统内存保护方案的系统中的存储器控制器和请求代理之间的桥接电路公开(公告)号：US20150186295A1
公开(公告)日：2015-07-02
申请号：US14142117
申请日：2013-12-27
申请人： Uday R. Savagaonkar , Siddhartha Chhabra , Men Long , Alpa T. Narendra Trivedi , Carlos Cornelas Omelas , Edgar Borrayo , Ramadass Nagarajan , Stanley Steve Kulick
发明人： Uday R. Savagaonkar , Siddhartha Chhabra , Men Long , Alpa T. Narendra Trivedi , Carlos Cornelas Omelas , Edgar Borrayo , Ramadass Nagarajan , Stanley Steve Kulick
CPC分类号： G06F12/1408 , G06F12/1441 , G06F21/74 , G06F2212/1052
摘要： A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a protected region and a non protected region. The processor includes a protection engine to protect against active and passive attacks. The processor includes an encryption/decryption engine to protect against passive attacks. The protection engine includes bridge circuitry coupled between the memory controller and the one or more processing cores. The bridge circuitry is also coupled to the protection engine and the encryption/decryption engine. The bridge circuitry is to route first requests directed to the protected region to the protection engine and to route second requests directed to the non protected region to the encryption/decryption engine.
摘要翻译： 描述了包括一个或多个处理核心的处理器。 处理器包括与具有受保护区域和非保护区域的系统存储器接口的存储器控制器。 该处理器包括保护引擎，以防止主动和被动攻击。 该处理器包括一个加密/解密引擎，以防止被动攻击。 保护引擎包括耦合在存储器控制器和一个或多个处理核心之间的桥接电路。 桥接电路还耦合到保护引擎和加密/解密引擎。 桥接电路是将定向到保护区域的第一请求路由到保护引擎，并将定向到非保护区域的第二请求路由到加密/解密引擎。
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公开(公告)号：US20080162799A1
公开(公告)日：2008-07-03
申请号：US11648483
申请日：2006-12-28
申请人： Bryan Spry , Nagi Aboulenein , Steve Kulick
发明人： Bryan Spry , Nagi Aboulenein , Steve Kulick
IPC分类号： G06F13/14
CPC分类号： G06F13/1642
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes a scheduler to schedule memory transactions to the DIMM and a write address queue to accumulate the write requests while the memory controller is operating in a first mode and to release the write requests to the scheduler whenever the memory controller is operating in a second mode.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括调度器，用于在存储器控制器以第一模式操作时调度到DIMM的存储器事务和写入地址队列以累积写请求，并且每当存储器控制器在 第二模式。
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