Image synthesizing device and image conversion device for synthesizing and displaying an NTSC or other interlaced image in any region of a VCA or other non-interlaced image
    1.
    发明授权
    Image synthesizing device and image conversion device for synthesizing and displaying an NTSC or other interlaced image in any region of a VCA or other non-interlaced image 失效
    图像合成装置和图像转换装置,用于在VCA或其它非隔行扫描图像的任何区域中合成和显示NTSC或其它隔行扫描图像

    公开(公告)号:US06356314B1

    公开(公告)日:2002-03-12

    申请号:US09380811

    申请日:1999-09-09

    申请人: Makoto Takebe

    发明人: Makoto Takebe

    IPC分类号: H04N545

    摘要: Provided is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display 9, wherein this image synthesizing device comprises a frame memory with which the data in the synthesis and display region P out of the sub-image data is continuously stored in the order of input, after which the stored sub-image data is read out when the scanning address of the main image data is an address corresponding to the display region Q, and a selector 4 with which the main image data displayed on the display 9 and the sub-image data continuously and sequentially read out from the frame memory are inputted, and when the scanning address of the main image data is an address corresponding to the display region Q, the selected channel is switched from main image data to the sub-image data and outputted to the display 9 where this sub-image data is displayed, which allows the capacity of the frame memory used for image synthesis to be smaller, and allows the sub-image to be reduced or magnified at the desired scale factor.

    摘要翻译: 提供了一种图像合成装置,其在合成显示在显示器9上的主图像的特定显示区域Q中合成并显示子图像的特定显示区域P,其中该图像合成装置包括帧存储器, 子图像数据中的合成和显示区域P中的数据以输入的顺序连续存储,之后当主图像数据的扫描地址是对应于地址的地址时,存储的子图像数据被读出 显示区域Q和从显示器9显示的主图像数据和从帧存储器连续顺序读出的子图像数据的选择器4被输入,并且当主图像数据的扫描地址是地址 对应于显示区域Q,所选择的通道从主图像数据切换到子图像数据,并输出到显示器9,显示该子图像数据,这允许容量o f用于图像合成的帧存储器较小,并允许以所需的比例因子减小或放大子图像。

    Image data memory control unit
    2.
    发明授权
    Image data memory control unit 失效
    图像数据存储器控制单元

    公开(公告)号:US5678035A

    公开(公告)日:1997-10-14

    申请号:US588630

    申请日:1996-01-19

    申请人: Makoto Takebe

    发明人: Makoto Takebe

    CPC分类号: G09G5/393 G09G5/022

    摘要: An image data memory control unit for storing the image data of a plurality of planes in a multiport video memory including a memory component having a random port for reading and writing data therethrough in response to input address signals and a register component having a serial port for outputting data that have been stored in the memory component serially in sequence from the lower address in synchronicity with input clock signals, comprises an image processor for outputting address signals in which the most significant bit portion is a plane recognition bit portion that recognizes the plurality of planes, and for outputting the image data of the plurality of planes therethrough to the multiport video memory in response to the address signals; and address conversion unit for converting the address signals output from the image processor so that the plane recognition bit portion is moved to the least significant bit portion, and the remaining bits are shifted to higher significant bits following the least significant bit portion.

    摘要翻译: 一种图像数据存储器控制单元,用于将多个平面的图像数据存储在多端口视频存储器中,该多端口视频存储器包括具有用于响应于输入地址信号而通过其读取和写入数据的随机端口的存储器组件,以及具有串行端口的寄存器组件 从与下一个地址顺序地输出存储在存储器组件中的数据与输入时钟信号同步地输出的数据包括用于输出地址信号的图像处理器,其中最高有效位部分是识别多个 平面,并且用于响应于地址信号将多个平面的图像数据输出到多端口视频存储器; 以及地址转换单元,用于转换从图像处理器输出的地址信号,使得平面识别比特部分移动到最低有效位部分,并且剩余比特被移位到最低有效位部分之后的较高有效位。

    Serial controller
    3.
    发明授权
    Serial controller 失效
    串行控制器

    公开(公告)号:US5461617A

    公开(公告)日:1995-10-24

    申请号:US861862

    申请日:1992-06-17

    CPC分类号: H04L12/43 H04L12/423 H04Q9/14

    摘要: A serial controller in which nodes to which are connected one or a plurality of sensors and one or a plurality of actuators are connected in series in the form of a closed loop including a main controller which sends data frame signals including a first special code, a second special code and output data for the actuators. Each of the nodes adds the data received from its associated sensor to the end of the first special code and picks up the output data for its associated actuator from the end of the second special code. The main controller controls the interval for sending the data frame signals depending upon the number of sensors and the number of actuators detected based on the initial frame signal that includes the first special code, the second special code and data for detecting the number of actuators, in order to improve the transmission efficiency and to carry out the control in real time.

    摘要翻译: PCT No.PCT / JP90 / 01707 Sec。 371日期:1992年6月17日 102(e)日期1992年6月17日PCT 1990年12月26日PCT PCT。 公开号WO91 / 10306 PCT 日期1991年7月11日。一种串行控制器,其中连接有一个或多个传感器的节点和一个或多个致动器以闭环的形式串联连接,包括主控制器,其发送数据帧信号 包括第一个特殊代码,第二个特殊代码和执行器的输出数据。 每个节点将从其关联的传感器接收到的数据添加到第一特殊代码的末尾,并从第二个特殊代码的末尾拾取其相关致动器的输出数据。 主控制器根据传感器的数量和基于初始帧信号检测到的致动器的数量控制发送数据帧信号的间隔,该初始帧信号包括第一特殊码,第二特殊码和用于检测致动器数量的数据, 以提高传输效率并实时进行控制。

    Digital phase synchronizing apparatus
    4.
    发明授权
    Digital phase synchronizing apparatus 失效
    数字相位同步装置

    公开(公告)号:US06404833B1

    公开(公告)日:2002-06-11

    申请号:US09156890

    申请日:1998-09-18

    申请人: Makoto Takebe

    发明人: Makoto Takebe

    IPC分类号: H04L700

    CPC分类号: H04L7/0338

    摘要: A digital phase synchronizing apparatus delays sequentially a clock signal output from an oscillator, generates a plurality of delayed clock signals, selects a delayed clock signal that is synchronized with horizontal synchronizing signal HS from among the delayed clock signals using a change point detection circuit, and selects the output signal. Meanwhile, fine delay circuit further delays sequentially the selected delayed clock signal, generates a plurality of delayed clock signals, and selects a delayed clock signal that corresponds to the setting of a rotary dip switch as the system clock, thereby to efficiently acquire phase synchronization of the clock signal with the input signal without being affected by the signal characteristics of the input signal.

    摘要翻译: 数字相位同步装置顺序地延迟从振荡器输出的时钟信号,产生多个延迟的时钟信号,使用变化点检测电路从延迟时钟信号中选择与水平同步信号HS同步的延迟时钟信号,以及 选择输出信号。 同时,精细延迟电路进一步顺序地延迟所选择的延迟时钟信号,产生多个延迟的时钟信号,并且选择与旋转dip开关的设置相对应的延迟的时钟信号作为系统时钟,从而有效地获取相位同步 具有输入信号的时钟信号不受输入信号的信号特性的影响。

    Binary subtraction device
    5.
    发明授权
    Binary subtraction device 失效
    二进制减法器

    公开(公告)号:US5784308A

    公开(公告)日:1998-07-21

    申请号:US751796

    申请日:1996-11-18

    CPC分类号: H04L12/43 H04L12/423 H04Q9/14

    摘要: For arithmetically combining the values of two numbers, for example adding and subtracting, comprising a data deletion system for deleting values from input data and outputting the result. The system has a deletion number detection apparatus for finding a value on the basis of input data and output data, wherein an output data number setting device sets the bits of an output data number to be all "1" in logical value prior to sending that number to a down counter which subtracts the output number from the input number for the result.

    摘要翻译: 用于算术组合两个数字的值,例如加法和减法,包括用于从输入数据中删除值并输出结果的数据删除系统。 该系统具有用于根据输入数据和输出数据找到值的删除号码检测装置,其中输出数据号码设置装置在发送该数据号码设置装置之前将逻辑值中的所有“1”的输出数据号的比特设置为全部 数字到递减计数器,从结果的输入数字中减去输出数字。

    Asynchronous data transmission system
    6.
    发明授权
    Asynchronous data transmission system 失效
    异步数据传输系统

    公开(公告)号:US5502822A

    公开(公告)日:1996-03-26

    申请号:US938037

    申请日:1992-11-12

    申请人: Makoto Takebe

    发明人: Makoto Takebe

    摘要: An asynchronous data transmission system for asynchronously transmitting data from a first system controller to a second system controller in which a memory for holding therein data to be transmitted has a duplex structure including first and second memories, output data of the first system controller is alternately written into the first and second memories in response to the data transmission of the first system controller, the reading operation of the second system controller is carried out over one of the memories over which the writing operation of the first system controller has been completed, the next writing operation of the first system controller is carried out over the other one of the memories.

    摘要翻译: PCT No.PCT / JP91 / 00632 Sec。 371日期:1992年11月12日 102(e)日期1992年11月12日PCT 1991年5月14日提交PCT公布。 WO91 / 18346 PCT公开号 日期:1991年11月28日。一种用于将数据从第一系统控制器异步传输到第二系统控制器的异步数据传输系统,其中用于保存要发送的数据的存储器具有包括第一和第二存储器的双工结构, 第一系统控制器响应于第一系统控制器的数据传输被交替地写入第一和第二存储器中,第二系统控制器的读取操作在第一系统的写操作的一个存储器中执行 控制器已经完成,第一系统控制器的下一个写入操作在另一个存储器上执行。

    Apparatus for carrying out serial control
    7.
    发明授权
    Apparatus for carrying out serial control 失效
    实现串行控制的装置

    公开(公告)号:US5095417A

    公开(公告)日:1992-03-10

    申请号:US459811

    申请日:1990-01-12

    IPC分类号: H04L12/423

    CPC分类号: H04L12/423

    摘要: This apparatus for carrying out serial control comprises a plurality of node controllers each including a group of sensors (21S to 2nS), a group of actuators (21A to 2nA) or the like terminal components and a main controller for controlling the node controllers and the terminal components in an annular configuration or in a daisychain-shaped configuration. The main controller sends a frame signal which includes a first identification code (STI) indicative of the head position of sensor data and a second identification code (STO) indicative of the head position of actuator controlling data in one frame. Each node controller including a group of sensors feeds its own sensor data to a location just behind the first identification code of the received frame signal and sends to the subsequent stage the frame signal delayed by a length of the sensor data having the received frame signal fed thereto, subsequent to the signal having the sensor data fed thereto. Further, each node controller including a group of actuators extracts its own actuator control data from a location just behind a second identification code of the received frame signal and then sends the frame signal having the actuator control data extracted therefrom, subsequent to the frame signal which has been delayed by a length equivalent to the actuator control data having the received frame signal extracted therefrom.

    摘要翻译: PCT No.PCT / JP89 / 00494 Sec。 371 1990年1月12日第 102(e)日期1990年1月12日PCT提交1989年5月16日PCT公布。 WO89 / 11763 PCT出版物 该串行控制装置包括多个节点控制器,每个节点控制器包括一组传感器(21S至2nS),一组致动器(21A至2nA)或类似终端组件,以及主控制器 用于控制节点控制器和终端组件为环形配置或菊花链形状的配置。 主控制器发送帧信号,该帧信号包括指示传感器数据的头位置的第一识别码(STI)和表示一帧中的致动器控制数据的头位置的第二识别码(STO)。 包括一组传感器的每个节点控制器将其自己的传感器数据馈送到紧接在接收到的帧信号的第一识别码之后的位置,并将延迟了接收到的帧信号的传感器数据的长度延迟到后一级 在传送数据的信号之后。 此外,包括一组致动器的每个节点控制器从恰好在接收到的帧信号的第二识别码之后的位置提取其自己的致动器控制数据,然后在帧信号之后发送具有从其中提取的致动器控制数据的帧信号, 已经延迟了与从其中提取的接收帧信号的致动器控制数据相当的长度。

    Data input control device for serial controller
    8.
    发明授权
    Data input control device for serial controller 失效
    串行控制器数据输入控制装置

    公开(公告)号:US5479421A

    公开(公告)日:1995-12-26

    申请号:US866169

    申请日:1992-06-24

    申请人: Makoto Takebe

    发明人: Makoto Takebe

    CPC分类号: H04J3/0629 H04Q9/14

    摘要: A data input control device for a serial controller wherein a plurality of nodes each having one or a plurality of sensors connected thereto are serially connected to each other with a main controller included therein, the main controller delivers a predetermined data frame signal at a period sufficiently shorter than the variation interval of data detected by the nodes, and each node serves to add to the data frame signal the data from sensors connected to the node. The main controller compares the sensor data contained in the data frame signal inputted thereinto for predetermined times on receipt of a data frame signal, and takes thereinto the sensor data as true data only when the results derived from the comparisons performed by the predetermined times coincide with each other. Therefore, errors caused over the whole path through which the data outputted from the sensors are inputted into the main controller via the respective nodes can be detected.

    摘要翻译: PCT No.PCT / JP90 / 01724 Sec。 371日期:1992年6月24日 102(e)日期1992年6月24日PCT 1990年12月27日PCT PCT。 公开号WO91 / 10302 日期:1991年7月11日。一种用于串行控制器的数据输入控制装置,其中,具有连接到其上的一个或多个传感器的多个节点通过其中包括的主控制器彼此串联连接,主控制器递送预定 数据帧信号在足够短于由节点检测的数据的变化间隔的周期内,并且每个节点用于向数据帧信号添加来自连接到该节点的传感器的数据。 主控制器在接收到数据帧信号时将输入到其中的数据帧信号中包含的传感器数据进行比较预定次数,并且只有当从预定时间执行的比较导出的结果与预定时间一致时将传感器数据作为真实数据 彼此。 因此,可以检测在从传感器输出的数据经由各个节点输入到主控制器的整个路径上引起的错误。

    Error display device of data transmission system
    9.
    发明授权
    Error display device of data transmission system 失效
    数据传输系统显示设备错误

    公开(公告)号:US5357517A

    公开(公告)日:1994-10-18

    申请号:US862553

    申请日:1992-06-23

    申请人: Makoto Takebe

    发明人: Makoto Takebe

    IPC分类号: H04L1/00 H04L5/22 H04L12/26

    CPC分类号: H04L43/00 H04L12/2602

    摘要: An error display device of a data transmission system in which a plurality of nodes are connected to a main controller to transmit data, the main controller being adapted to discriminate an error content and an error position from an error signal contained in a data frame signal transmitted from the nodes and to display the error content and position. Since it is so arranged that the storage content of temporary memory for temporarily storing therein a signal corresponding to the error content and the error position is not updated each time the error signal is inputted but updated intermittently according to an operator's instruction, even when errors frequently take place at a multiplicity of locations, that is, even when it is difficult for an operator to confirm error display contents, the operator can reliably confirm the error contents.

    摘要翻译: PCT No.PCT / JP90 / 01706 Sec。 371日期:1992年6月23日 102(e)日期1992年6月23日PCT 1990年12月26日PCT PCT。 WO91 / 10301 PCT出版物 日期1991年7月11日。一种数据传输系统的错误显示装置,其中多个节点连接到主控制器以发送数据,主控制器适于从错误信号中识别错误内容和错误位置 包含在从节点发送的数据帧信号中并显示错误内容和位置。 由于这样设置使得每当输入错误信号但是根据操作者的指令间歇地更新时,临时存储与其对应的错误内容和错误位置的信号的临时存储器的存储内容即使是经常地错误地更新 发生在多个位置,也就是说,即使操作者难以确认错误显示内容,操作者可以可靠地确认错误内容。

    Data extracting circuit for serial control apparatus
    10.
    发明授权
    Data extracting circuit for serial control apparatus 失效
    用于串行控制装置的数据提取电路

    公开(公告)号:US5204865A

    公开(公告)日:1993-04-20

    申请号:US571539

    申请日:1990-08-27

    IPC分类号: H04L12/423

    CPC分类号: H04L12/423

    摘要: A serial control apparatus includes a main controller (2) and a plurality of nodes (3) each serving as an auxiliary controller normally serially arranged on a loop-shaped signal transmission line (1). Each node (3) extracts data for the present node among from the data delivered from the main controller (2) as time elapses so as to allow the terminal units (A) associated with the present node to be properly controlled. In addition, the node inserts the output data from the terminal units (A) into a time slot corresponding to the present node and then delivers to the signal transmission line (1) the output data which in turn are transferred to the main controller (2) via other nodes on the downstream side. To assure that the data extracting circuit operates properly, two latching circuits, i.e., first and second latching circuits (311, 312 to 315) are serially arranged in a signal passage by way of which the extracted data are fed to a driver (316) for the corresponding terminal units.

    摘要翻译: PCT No.PCT / JP89 / 00208 Sec。 371日期1990年8月9日 102(e)日期1990年8月9日PCT提交1989年2月28日PCT公布。 出版物WO89 / 08361 日期:1989年9月8日。一种串行控制装置包括主控制器(2)和多个节点(3),每个节点(3)均用作正常串联布置在环形信号传输线(1)上的辅助控制器。 每个节点(3)随着时间的推移从主控制器(2)发送的数据中提取当前节点的数据,以允许适当地控制与本节点相关联的终端单元(A)。 此外,节点将来自终端单元(A)的输出数据插入到与本节点对应的时隙中,然后将输出数据传送到信号传输线(1),输出数据又被传送到主控制器(2) )通过下游侧的其他节点。 为了确保数据提取电路正常工作,两个锁存电路,即第一和第二锁存电路(311,312至315)被串行地布置在信号通道中,通过该信号通道将提取的数据馈送到驱动器(316) 为相应的终端单元。