公开(公告)号：US6058252A

公开(公告)日：2000-05-02

申请号：US910803

申请日：1997-08-13

申请人： Mark D. Noll ,  Kenneth E. Scott ,  Robert L. Walker

发明人： Mark D. Noll ,  Kenneth E. Scott ,  Robert L. Walker

IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L21/70

CPC分类号： G06F17/5068 ,  G06F17/5031

摘要： A computer system and computer implemented method for deriving constraints with which to direct automatic integrated circuit layout is disclosed. The present invention is particularly adapted for use in the design of large integrated circuits with complex synchronous timing behavior. Preferably, the invented computer system includes means for storing a netlist data structure within a storage means is provided, the netlist data structure representing a circuit configuration having a plurality of circuit elements and representing static timing information for the circuit configuration; means for selecting specified circuit elements to be used for generating the layout constraints, whereby the specified circuit elements that are selected are fewer than, i.e. represent a proper subset of, the plurality of circuit elements of the circuit configuration; means for identifying a most critical path through each of the specified circuit elements based upon the static timing information, whereby preferably the most critical path is that path having the least slack defined as the difference between a required time at which a signal should reach the specified circuit element and an arrival time at which the signal is expected to reach the specified circuit element; and means for generating layout constraints from the most critical path through each of the specified circuit elements, whereby at least one constraint is generated covering each of the specified circuit elements. Also disclosed is a feature whereby any paths that do no meet specified filter criteria, and paths that are duplicates of others, are discarded, thereby retaining only irredudant critical paths on which to base layout constraints.

摘要翻译： 公开了一种用于导出用于引导自动集成电路布局的约束的计算机系统和计算机实现的方法。 本发明特别适用于设计具有复杂同步定时特性的大型集成电路。 优选地，本发明的计算机系统包括用于在存储装置内存储网表数据结构的装置，网表数据结构表示具有多个电路元件并表示电路配置的静态定时信息的电路配置; 用于选择要用于产生布局约束的指定电路元件的装置，由此所选择的指定电路元件少于，即表示电路配置的多个电路元件的适当子集; 用于基于静态定时信息识别通过每个指定电路元件的最关键路径的装置，其中优选地，最关键的路径是具有最小松弛的路径被定义为信号到达指定的所需时间之间的差 电路元件和预期到达指定电路元件的到达时间; 以及用于从通过每个指定电路元件的最关键路径产生布局约束的装置，由此产生覆盖每个指定电路元件的至少一个约束。 还公开了一种特征，其中不符合指定的过滤标准的任何路径和与其他路由重复的路径被丢弃，从而仅保留基于布局约束的不必要的关键路径。