公开(公告)号：US6058252A

公开(公告)日：2000-05-02

申请号：US910803

申请日：1997-08-13

申请人： Mark D. Noll ,  Kenneth E. Scott ,  Robert L. Walker

发明人： Mark D. Noll ,  Kenneth E. Scott ,  Robert L. Walker

IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L21/70

CPC分类号： G06F17/5068 ,  G06F17/5031

摘要： A computer system and computer implemented method for deriving constraints with which to direct automatic integrated circuit layout is disclosed. The present invention is particularly adapted for use in the design of large integrated circuits with complex synchronous timing behavior. Preferably, the invented computer system includes means for storing a netlist data structure within a storage means is provided, the netlist data structure representing a circuit configuration having a plurality of circuit elements and representing static timing information for the circuit configuration; means for selecting specified circuit elements to be used for generating the layout constraints, whereby the specified circuit elements that are selected are fewer than, i.e. represent a proper subset of, the plurality of circuit elements of the circuit configuration; means for identifying a most critical path through each of the specified circuit elements based upon the static timing information, whereby preferably the most critical path is that path having the least slack defined as the difference between a required time at which a signal should reach the specified circuit element and an arrival time at which the signal is expected to reach the specified circuit element; and means for generating layout constraints from the most critical path through each of the specified circuit elements, whereby at least one constraint is generated covering each of the specified circuit elements. Also disclosed is a feature whereby any paths that do no meet specified filter criteria, and paths that are duplicates of others, are discarded, thereby retaining only irredudant critical paths on which to base layout constraints.

摘要翻译： 公开了一种用于导出用于引导自动集成电路布局的约束的计算机系统和计算机实现的方法。 本发明特别适用于设计具有复杂同步定时特性的大型集成电路。 优选地，本发明的计算机系统包括用于在存储装置内存储网表数据结构的装置，网表数据结构表示具有多个电路元件并表示电路配置的静态定时信息的电路配置; 用于选择要用于产生布局约束的指定电路元件的装置，由此所选择的指定电路元件少于，即表示电路配置的多个电路元件的适当子集; 用于基于静态定时信息识别通过每个指定电路元件的最关键路径的装置，其中优选地，最关键的路径是具有最小松弛的路径被定义为信号到达指定的所需时间之间的差 电路元件和预期到达指定电路元件的到达时间; 以及用于从通过每个指定电路元件的最关键路径产生布局约束的装置，由此产生覆盖每个指定电路元件的至少一个约束。 还公开了一种特征，其中不符合指定的过滤标准的任何路径和与其他路由重复的路径被丢弃，从而仅保留基于布局约束的不必要的关键路径。

公开(公告)号：US06535549B1

公开(公告)日：2003-03-18

申请号：US09395699

申请日：1999-09-14

申请人： Kenneth E. Scott ,  Elizabeth B. Olasz

发明人： Kenneth E. Scott ,  Elizabeth B. Olasz

IPC分类号： H04L2722

CPC分类号： H04L27/3872 ,  H04L7/027 ,  H04L2007/047 ,  H04L2027/003 ,  H04L2027/0046 ,  H04L2027/0087

摘要： A method and telecommunication system for tracking the carrier phase of a received signal includes the addition of a pilot signal to the data component of the signal prior to modulation and transmission. The pilot signal is specified to have a frequency equal to the inverse of twice a data symbol interval with zero crossings positioned at the midpoint of each symbol interval to avoid interference with the data. The received signal is demodulated to produce a complex data signal from which the pilot signal is detected to provide an estimate of the phase error in the complex data signal. The elimination of the phase error from the complex data signal is accomplished through a corrective phase shift that is equal and opposite to the estimated phase error. A sample timing estimate may also be obtained in a similar manner.

摘要翻译： 用于跟踪接收信号的载波相位的方法和电信系统包括在调制和传输之前向信号的数据分量添加导频信号。 导频信号被指定为具有等于数据符号间隔两倍的频率的频率，其中零交叉位于每个符号间隔的中点处，以避免与数据的干扰。 接收的信号被解调以产生复数数据信号，从该数据信号中检测导频信号以提供复数数据信号中的相位误差的估计。 通过与估计的相位误差相等且相反的校正相移来实现从复数数据信号中消除相位误差。 也可以以类似的方式获得采样定时估计。

公开(公告)号：US5282228A

公开(公告)日：1994-01-25

申请号：US804424

申请日：1991-12-09

申请人： Kenneth E. Scott ,  Michael Kaube ,  Kiomars Anvari

发明人： Kenneth E. Scott ,  Michael Kaube ,  Kiomars Anvari

IPC分类号： H04L7/02 ,  H04L27/00 ,  H04L27/233 ,  H04L27/06

CPC分类号： H04L7/0054 ,  H04L27/2332 ,  H04L2027/003 ,  H04L2027/0055

摘要： A technique for correcting the sampling time and carrier frequency error in a receiver for digitally modulated signals. Discrete-time, complex-valued samples of the incoming signal are fed to a pair of non-linear operators such as correlators. The first correlator provides a signal having a first phase component related to the symbol timing error and a second phase component related to the carrier frequency error. The second correlator provides a signal having a first phase component related to the symbol timing error and a second phase component related to the negative of the carrier frequency error. The phase components are then separated and detected to extract an estimate of the symbol timing error and the carrier frequency error. In the preferred embodiment, the complex-valued samples are frequency-shifted, before being fed to the correlators, so that the phase components of interest appear at zero frequency. The invention satisfactorily demodulates transmitted digital signals in applications, such as cellular time-division multiple access (TDMA), where they are susceptible to multipath fading.

摘要翻译： 一种用于校正数字调制信号的接收机中的采样时间和载波频率误差的技术。 输入信号的离散时间，复值样本被馈送到一对非线性运算符，例如相关器。 第一相关器提供具有与码元定时误差相关的第一相位分量的信号和与载波频率误差有关的第二相位分量。 第二相关器提供具有与符号定时误差相关的第一相位分量的信号和与载波频率误差的负相关的第二相位分量。 然后分离和检测相位分量以提取符号定时误差和载波频率误差的估计。 在优选实施例中，复值样本在被馈送到相关器之前进行频移，使得感兴趣的相位分量出现在零频率。 本发明在诸如蜂窝时分多址（TDMA）等应用中令人满意地解调发射的数字信号，其中它们易受多径衰落的影响。

公开(公告)号：US4322927A

公开(公告)日：1982-04-06

申请号：US71924

申请日：1979-09-04

申请人： Kenneth E. Scott

发明人： Kenneth E. Scott

IPC分类号： B28B11/00 ,  E04F11/00 ,  E04F11/16

CPC分类号： B28B11/00 ,  E04F11/00 ,  E04F11/16

摘要： A method of making a closed-tread staircase, and of making steps for such a staircase. The tread and riser of each step are each made from a rebated, grooved slab; the rebates on tread and riser are mated to form a joint, which is secured by a joining strip of `V`-shaped cross-section formed with flanges which are forced into the slab grooves. Steps are joined together in the same manner, and a staircase formed by supporting a series of steps upon two or more stair carriages, each carriage comprising a stringer with a series of spaced cleats secured to one side. Each cleat provides a horizontal tread-supporting portion and a vertical riser-supporting portion. Each stair carriage may be made using apparatus which provides means for supporting and indexing a stringer and supporting each cleat at a predetermined angle while cleat and stringer are secured together.

摘要翻译： 一种制作封闭胎面楼梯的方法，以及制造这种楼梯的步骤。 每个步骤的胎面和立管均由一个带有凹槽的开槽板制成; 胎面和提升管上的槽口配合形成接头，该接头通过形成有凸缘的“V”形横截面的接合带固定，凸缘被迫进入板坯槽。 步骤以相同的方式连接在一起，并且通过在两个或更多个楼梯支架上支撑一系列步骤形成的楼梯，每个托架包括具有固定到一侧的一系列间隔的防滑板的纵梁。 每个防滑板提供水平的胎面支撑部分和垂直的提升管支撑部分。 每个楼梯托架可以使用装置来制造，该装置提供用于支撑和索引桁条并且以预定角度支撑每个防滑钉的装置，同时将夹板和纵梁固定在一起。

公开(公告)号：USD260492S

公开(公告)日：1981-09-01

申请号：US49263

申请日：1979-06-18

申请人： Kenneth E. Scott

设计人： Kenneth E. Scott

公开(公告)号：US5422917A

公开(公告)日：1995-06-06

申请号：US245

申请日：1993-01-04

申请人： Kenneth E. Scott

发明人： Kenneth E. Scott

IPC分类号： H03J7/02 ,  H04L7/02 ,  H04L7/04 ,  H04L27/00 ,  H04L7/00 ,  H04L25/36 ,  H04L25/40

CPC分类号： H03J7/02 ,  H04L2027/0065

摘要： A receiver (10) for extracting complex values by reference to a local frequency reference determines the frequency offset between a local oscillator (16) and the carrier by employing a circuit (40) for determining a "phase rotation." When a record of the input signal is determined to have resulted from a predetermined reference sequence of complex values, the phase-rotation circuit (40) compares the phases of complex values extracted from this record with corresponding symbols of the reference sequence. By comparing this difference for one part of the sequence with that for another, circuitry (38, 50, 52, 53, 54) in the receiver infers the frequency offset between the transmitter reference and the receiver reference, and a complex multiplier (34) compensates for this offset by multiplying the successive complex-valued samples by a complex exponential whose frequency is the negative of the frequency offset.

摘要翻译： 通过参考本地频率参考来提取复数值的接收器（10）通过采用用于确定“相位旋转”的电路（40）来确定本地振荡器（16）和载波之间的频率偏移。 当确定输入信号的记录是由预定的复数值的参考序列导致时，相位旋转电路（40）将从该记录提取的复数值的相位与参考序列的相应符号进行比较。 通过将该序列的一部分与另一部分的差异进行比较，接收机中的电路（38,50,52,53,54）推断发射机参考和接收机参考之间的频率偏移，以及复数乘法器（34） 通过将连续的复值样本乘以频率为频率偏移的负的复指数，来补偿该偏移。

公开(公告)号：US5328562A

公开(公告)日：1994-07-12

申请号：US520198

申请日：1990-05-09

申请人： Andrew J. Rafferty ,  Kenneth E. Scott

发明人： Andrew J. Rafferty ,  Kenneth E. Scott

IPC分类号： B27N1/00 ,  C08H8/00 ,  C08L97/02 ,  D21B1/36 ,  D21C1/02 ,  D21C1/10 ,  D21H11/00 ,  D21J1/16 ,  D21B1/12

CPC分类号： C08H8/00 ,  B27N1/00 ,  C08L97/02 ,  D21B1/36 ,  D21C1/02 ,  D21C1/10

摘要： An energy efficient process for hydrolyzing lignocellulosic materials which comprises using a primary system by providing a start-up energy input to operating saturated steam conditions and thereafter operating the primary system with substantially constant energy input, the condition of the hydrolysing saturated steam being controlled by water injection and/or steam bleeding from the primary system. The dwell time of the solids stream in the primary system is controlled by controlling its passage with flashing off of steam into a secondary system where drying occurs together with some small measure of hydrolysis in a lower pressure superheated steam environment, there being an energy input into the secondary system using steam bled from the primary system. The output solids material stream is preferably capable of being self polymerized into a formed shape eg a board.

摘要翻译： 用于水解木质纤维素材料的能量有效的方法，其包括通过提供启动能量输入来运行饱和蒸汽条件并随后以基本上恒定的能量输入来操作初级系统来使用主要系统，水解饱和蒸汽的条件由水控制 注射和/或蒸汽从主系统出血。 初级系统中的固体物流的停留时间通过控制其通过蒸汽闪蒸进入二次系统来控制，其中干燥与低压过热蒸汽环境中的一些小水解一起进行，其中有能量输入 二次系统使用从主系统排出的蒸汽。 输出固体物质流优选能够自聚合为成形形状，例如板。

公开(公告)号：US5111413A

公开(公告)日：1992-05-05

申请号：US328427

申请日：1989-03-24

申请人： Richard W. Lazansky ,  Thomas R. Miller ,  David R. Coelho ,  Kenneth E. Scott ,  Alec G. Stanculescu

发明人： Richard W. Lazansky ,  Thomas R. Miller ,  David R. Coelho ,  Kenneth E. Scott ,  Alec G. Stanculescu

IPC分类号： G06F11/25 ,  G06F17/50

CPC分类号： G06F17/5022

摘要： A simulation system for circuit design is disclosed. The system couples a schematic editor and simulator to allow incremental changes to a design under test without requiring prior shutdown of the simulator. The system uses a method which permits a wide range of changes to the design and provides a resulting netlist for the changed design. Changes can be made to the schematic which include changes in hierarchy, addition or deletion of components (including hierarchical components), addition or deletion of signals at any level within the design hierarchy, addition or deletion of interconnections of components at any level of hierarchy within the design, addition and deletion of interface ports for any component type, substitution of a new component for an existing one (including swapping hierarchical and behavioral descriptions), and alteration of parametric data such as device delay timing. The simulation continues to run after design changes are made. The method may be used in conjunction with hardware modeling systems.

摘要翻译： 公开了一种用于电路设计的仿真系统。 该系统将一个原理图编辑器和模拟器耦合到允许对被测设计进行增量更改，而无需先前关闭模拟器。 该系统使用一种允许对设计进行大范围更改的方法，并为更改后的设计提供最终的网表。 可以对原理图进行更改，包括层次结构的更改，组件的添加或删除（包括分层组件），设计层级内任何级别的信号的添加或删除，添加或删除任何层级结构内的组件互连 任何组件类型的接口端口的设计，添加和删除，对现有组件的新组件的替换（包括交换层次结构和行为描述）以及参数数据的更改，如设备延迟时序。 在进行设计更改后，仿真继续运行。 该方法可以与硬件建模系统结合使用。

公开(公告)号：US3446109A

公开(公告)日：1969-05-27

申请号：US3446109D

申请日：1967-01-09

申请人： BRUCE T SCOTT ,  KENNETH E SCOTT

发明人： SCOTT BRUCE T ,  SCOTT KENNETH E

IPC分类号： G09B15/08

CPC分类号： G09B15/08