-
公开(公告)号：US08196074B2
公开(公告)日：2012-06-05
申请号：US12406439
申请日：2009-03-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译： 一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。 例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。
-
2.发明授权Methods and apparatus for reducing command processing latency while maintaining coherence 失效减少命令处理延迟同时保持一致性的方法和装置公开(公告)号：US08112590B2
公开(公告)日：2012-02-07
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。 第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。 响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。 提供了许多其他方面。
-
公开(公告)号：US20090178014A1
公开(公告)日：2009-07-09
申请号：US12406439
申请日：2009-03-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译： 一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。 例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。
-
4.发明授权Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree 失效用于设计用于匹配时钟树门控部分的逻辑扫描链的方法，装置和计算机程序产品公开(公告)号：US07543204B2
公开(公告)日：2009-06-02
申请号：US11191417
申请日：2005-07-28
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318583
摘要： Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.
摘要翻译： 提供了用于设计用于匹配时钟树的门控部分的逻辑扫描链的方法，装置和计算机程序产品。 时钟树包括多个部分，每个部分包括接收用于特定扫描链的全局时钟和链专用时钟控制信号的输入的门。 定义了多个扫描链，每个扫描链包括多个闩锁。 每个扫描链锁存器连接到相应的链专用时钟树部分。
-
5.发明授权Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain 有权用于实现扫描链特定控制信号作为扫描链的一部分的方法，装置和计算机程序产品公开(公告)号：US07475307B2
公开(公告)日：2009-01-06
申请号：US12023060
申请日：2008-01-31
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes a logic gate for combining a global clock control (THOLD) signal and the scan control signal. The scan control signal is routed around the register latch and including in a scan output vector including scan data output. Chain-specific control signals are eliminated from a clock control signal distribution tree used with the scan chain of the invention.
摘要翻译： 提供了一种用于实现扫描链特定控制信号作为扫描链的组成部分的方法，装置和计算机程序产品。 包括扫描数据输入和扫描控制信号的扫描输入矢量被施加到形成扫描链的寄存器锁存器。 寄存器锁存器包括用于组合全局时钟控制（THOLD）信号和扫描控制信号的逻辑门。 扫描控制信号围绕寄存器锁存器路由并包括在包括扫描数据输出的扫描输出向量中。 从与本发明的扫描链一起使用的时钟控制信号分配树中消除链特定控制信号。
-
6.发明授权Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout 失效基于物理布局的集成电路设计的功能定义的自动背面注释公开(公告)号：US07398505B2
公开(公告)日：2008-07-08
申请号：US11348877
申请日：2006-02-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
摘要翻译： 一种装置，程序产品和方法基于从功能定义生成的物理布局自动地回溯电路设计的功能定义。 电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号 功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。
-
公开(公告)号：US06745376B2
公开(公告)日：2004-06-01
申请号：US09954813
申请日：2001-09-17
申请人： Mark S. Fredrickson
发明人： Mark S. Fredrickson
IPC分类号： G06F945
CPC分类号： G06F17/5031
摘要： A method for graphically representing various types of timing relationships between signals in an electronic system. After a static timing analysis is performed on an electronic system, a set of timing waveforms is displayed. The present invention analyzes the timing relationships between the waveforms, then generates and adds a graphical symbol representing the type and characteristics of the timing relationship to the display.
摘要翻译： 一种用于图形化地表示电子系统中各种信号之间的定时关系的方法。 在电子系统上执行静态时序分析之后，显示一组定时波形。 本发明分析波形之间的定时关系，然后生成并添加表示定时关系的类型和特性的图形符号到显示器。
-
公开(公告)号：US09146835B2
公开(公告)日：2015-09-29
申请号：US13343809
申请日：2012-01-05
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译： 第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。 第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。 第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。 第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。 第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。
-
公开(公告)号：US20130179720A1
公开(公告)日：2013-07-11
申请号：US13343809
申请日：2012-01-05
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译： 第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。 第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。 第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。 第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。 第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。
-
公开(公告)号：US07302510B2
公开(公告)日：2007-11-27
申请号：US11239615
申请日：2005-09-29
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.
摘要翻译： 一个公平的分级仲裁器包括多个仲裁机制，每个仲裁机制按照请求者的轮询顺序转发请求者的获胜请求。 除了获胜请求之外，每个仲裁机制转发有效请求比特，有效请求比特提供关于哪个请求者发起当前获胜请求的信息，并且在一些实施例中，关于该特定仲裁机制来仲裁多少个单独的请求者。 公平的分级仲裁器以循环次序输出来自全套独立请求者的请求。
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.025 秒)
