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1.发明授权Methods and apparatus for reducing command processing latency while maintaining coherence 失效减少命令处理延迟同时保持一致性的方法和装置公开(公告)号：US08112590B2
公开(公告)日：2012-02-07
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。 第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。 响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。 提供了许多其他方面。
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公开(公告)号：US07302510B2
公开(公告)日：2007-11-27
申请号：US11239615
申请日：2005-09-29
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.
摘要翻译： 一个公平的分级仲裁器包括多个仲裁机制，每个仲裁机制按照请求者的轮询顺序转发请求者的获胜请求。 除了获胜请求之外，每个仲裁机制转发有效请求比特，有效请求比特提供关于哪个请求者发起当前获胜请求的信息，并且在一些实施例中，关于该特定仲裁机制来仲裁多少个单独的请求者。 公平的分级仲裁器以循环次序输出来自全套独立请求者的请求。
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公开(公告)号：US06181320B2
公开(公告)日：2001-01-30
申请号：US09136473
申请日：1998-08-19
申请人： Mark S. Fredrickson
发明人： Mark S. Fredrickson
IPC分类号： G09G536
CPC分类号： G06F17/5031
摘要： A computer-implemented method and computer program product or software tool for converting a timing graph produced by a static timing engine into a timing diagram and vice versa may be integrated with a static timing analysis tool or may be a stand-alone product. The timing graph is represented by a data structure having nodes that correspond to actual circuit nodes of a circuit simulated by the timing engine and arcs connecting the nodes that correspond to temporal relationships between points on the timing diagram waveforms, such as points at which state transitions occur. To convert a timing graph to a timing diagram, the data structure is traversed from node to node. State transitions are extracted from each node, and temporal relationships between the signals are extracted from each arc. A graphical representation of the timing diagram is then displayed. Alternatively, the timing diagram is output in a suitable file format, such as Timing Diagram Markup Language (TDML). The steps can be reversed to convert a timing diagram into a timing graph.
摘要翻译： 用于将由静态定时引擎产生的定时图转换成时序图，反之亦然的计算机实现的方法和计算机程序产品或软件工具可以与静态时序分析工具集成，或者可以是独立的产品。 定时图由具有对应于由定时引擎模拟的电路的实际电路节点的节点的数据结构表示，并且连接节点的弧线对应于时序图波形上的点之间的时间关系，例如状态转换 发生。 要将时序图转换为时序图，数据结构从节点到节点遍历。 从每个节点提取状态转换，并从每个弧提取信号之间的时间关系。 然后显示时序图的图形表示。 或者，时序图以合适的文件格式输出，例如时序图标记语言（TDML）。 可以颠倒这些步骤，将时序图转换为时序图。
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公开(公告)号：US07509611B2
公开(公告)日：2009-03-24
申请号：US11348970
申请日：2006-02-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译： 一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。 例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。
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5.发明申请TRADING PROPENSITY-BASED CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN 审中-公开电路设计中电路元件的交易基于特征的聚类公开(公告)号：US20080307281A1
公开(公告)日：2008-12-11
申请号：US12191654
申请日：2008-08-14
IPC分类号： G01R31/28
CPC分类号： G01R31/318357 , G01R31/318536 , G06F17/5045
摘要： An apparatus and program product utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.
摘要翻译： 装置和程序产品利用基于交易倾向的聚类算法来生成电路元件到集群或组的分配，以优化多个集群的空间分布。 例如，可以使用基于交易倾向的聚类来将电路元件（诸如具有扫描功能的锁存器）分配给单独的扫描链，以优化用于集成电路设计的扫描架构中的扫描链的布局。
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6.发明授权公开(公告)号：US07430699B2
公开(公告)日：2008-09-30
申请号：US11348907
申请日：2006-02-07
IPC分类号： G01R31/28
CPC分类号： G01R31/318357 , G01R31/318536 , G06F17/5045
摘要： An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.
摘要翻译： 装置，程序产品和方法利用基于交易倾向的聚类算法来生成电路元件到集群或组的分配，以优化多个集群的空间分布。 例如，可以使用基于交易倾向的聚类来将电路元件（诸如具有扫描功能的锁存器）分配给单独的扫描链，以优化用于集成电路设计的扫描架构中的扫描链的布局。
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7.发明申请AUTOMATIC BACK ANNOTATION OF A FUNCTIONAL DEFINITION OF AN INTEGRATED CIRCUIT DESIGN BASED UPON PHYSICAL LAYOUT 审中-公开基于物理布局的集成电路设计的功能定义的自动返回公开(公告)号：US20080141210A1
公开(公告)日：2008-06-12
申请号：US12031999
申请日：2008-02-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus and program product automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
摘要翻译： 基于从功能定义生成的物理布局，设备和程序产品自动返回注释电路设计的功能定义。 电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号 功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。
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8.发明申请METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SCAN-CHAIN-SPECIFIC CONTROL SIGNALS AS PART OF A SCAN CHAIN 有权用于执行扫描链特定控制信号作为扫描链的一部分的方法，装置和计算机程序产品公开(公告)号：US20080133992A1
公开(公告)日：2008-06-05
申请号：US12023060
申请日：2008-01-31
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes a logic gate for combining a global clock control (THOLD) signal and the scan control signal. The scan control signal is routed around the register latch and including in a scan output vector including scan data output. Chain-specific control signals are eliminated from a clock control signal distribution tree used with the scan chain of the invention.
摘要翻译： 提供了一种用于实现扫描链特定控制信号作为扫描链的组成部分的方法，装置和计算机程序产品。 包括扫描数据输入和扫描控制信号的扫描输入矢量被施加到形成扫描链的寄存器锁存器。 寄存器锁存器包括用于组合全局时钟控制（THOLD）信号和扫描控制信号的逻辑门。 扫描控制信号围绕寄存器锁存器路由并包括在包括扫描数据输出的扫描输出向量中。 从与本发明的扫描链一起使用的时钟控制信号分配树中消除链特定控制信号。
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9.发明授权Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain 有权用于实现扫描链特定控制信号作为扫描链的一部分的方法，装置和计算机程序产品公开(公告)号：US07350122B2
公开(公告)日：2008-03-25
申请号：US11266744
申请日：2005-11-03
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes a logic gate for combining a global clock control (THOLD) signal and the scan control signal. The scan control signal is routed around the register latch and including in a scan output vector including scan data output. Chain-specific control signals are eliminated from a clock control signal distribution tree used with the scan chain of the invention.
摘要翻译： 提供了一种用于实现扫描链特定控制信号作为扫描链的组成部分的方法，装置和计算机程序产品。 包括扫描数据输入和扫描控制信号的扫描输入矢量被施加到形成扫描链的寄存器锁存器。 寄存器锁存器包括用于组合全局时钟控制（THOLD）信号和扫描控制信号的逻辑门。 扫描控制信号围绕寄存器锁存器路由并包括在包括扫描数据输出的扫描输出向量中。 从与本发明的扫描链一起使用的时钟控制信号分配树中消除链特定控制信号。
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公开(公告)号：US08196074B2
公开(公告)日：2012-06-05
申请号：US12406439
申请日：2009-03-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译： 一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。 例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。
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