公开(公告)号：US08453097B2

公开(公告)日：2013-05-28

申请号：US13414522

申请日：2012-03-07

申请人： A. Martin Mallinson

发明人： A. Martin Mallinson

IPC分类号： G06F17/50

CPC分类号： G06F17/5063

摘要： A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve compound values having constant ratios to the initial elements and to each other is disclosed. The ratios between compound values can be held constant to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the ratios between values depend primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.

摘要翻译： 公开了一种用于产生和匹配名义上相同的初始元素的复杂串联和/或并联组合以实现具有与初始元素和彼此具有恒定比率的化合物值的方法和系统。 复合值之间的比率可以保持恒定到几乎任何所需的准确度，潜在的误差比在不同值的各个元件的构造中典型地降低。 由于初始元件名义上相同，所以值之间的比率主要取决于初始元件的连接，而不是它们的几何形状，并且因此保持实质上恒定，而与制造过程中的变化无关。

公开(公告)号：US20110231695A1

公开(公告)日：2011-09-22

申请号：US13117054

申请日：2011-05-26

申请人： Martin Mallinson

发明人： Martin Mallinson

IPC分类号： G06F1/08

CPC分类号： H03K5/135 ,  G06F1/025

摘要： An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.

摘要翻译： 开发替代电路的机会很明显。 与驱动数字频率发生器（DFG）的时钟相关的无伪影的简化电路在各种可调电子设备中非常有用。 本发明涉及数字频率产生。 特别地，本发明涉及一种用于数字生成具有相对于参考时钟信号的期望频率和两个整数的比率的脉冲流的方法和装置。 该方法通常适用于其比率不是整数的整数。 作为设备的DFG可以集成到简单的芯片上，而不需要片外滤波器。

公开(公告)号：US20110140743A1

公开(公告)日：2011-06-16

申请号：US12683137

申请日：2010-01-06

申请人： Andrew Martin Mallinson

发明人： Andrew Martin Mallinson

IPC分类号： H03B21/00 ,  G06G7/16

CPC分类号： G06F1/025

摘要： A digital frequency generator is described.

摘要翻译： 描述数字频率发生器。

公开(公告)号：US07379006B2

公开(公告)日：2008-05-27

申请号：US11538000

申请日：2006-10-02

申请人： Dustin D. Forman ,  A. Martin Mallinson ,  Simon Damphousse

发明人： Dustin D. Forman ,  A. Martin Mallinson ,  Simon Damphousse

IPC分类号： H03M1/66

CPC分类号： H03M1/822

摘要： The present invention relates to multi-bit to pulse width modulated signal conversion, with extensions to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to audio output.

摘要翻译： 本发明涉及多比特至脉宽调制信号转换，具有数模转换的扩展。 特别地，它适用于将诸如用于CD和DVD的脉冲编码调制信号转换成音频输出。

公开(公告)号：US07028070B2

公开(公告)日：2006-04-11

申请号：US10057087

申请日：2002-01-26

申请人： Andrew Martin Mallinson

发明人： Andrew Martin Mallinson

IPC分类号： G06G1/02

CPC分类号： H03H15/00 ,  G06G7/1928

摘要： An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

公开(公告)号：US06646585B2

公开(公告)日：2003-11-11

申请号：US10118224

申请日：2002-04-05

申请人： Andrew Martin Mallinson

发明人： Andrew Martin Mallinson

IPC分类号： H03M136

CPC分类号： H03M1/367

摘要： A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

摘要翻译： 一种差分输入闪存模数转换器，其中连接比较器阵列以比较通过在阻抗网络上施加差分输入信号产生的这种信号的抛物面分布中的参考信号。 优选地，比较器阵列包括至少两个多个比较器，第一多个比较器比较由第一步长分隔的参考节点对，而第二多个比较器比较由第二步长分隔的参考节点对。 甚至更优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时使转换器的可用比较范围最大化。 根据本发明的闪存转换器从输入提供增加的增益，而不会累积比较器输入电流，并且不牺牲参考信号的实际比较的数量。

公开(公告)号：US5233309A

公开(公告)日：1993-08-03

申请号：US819376

申请日：1992-01-09

申请人： Paul Spitalny ,  Martin Mallinson

发明人： Paul Spitalny ,  Martin Mallinson

IPC分类号： H03G1/00 ,  H03G3/00

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： A programmable gain amplifier including first and second gain elements are connected by an impedance selector which allows programmability of the gain of both gain elements. The impedance selector is connected in series with the output of the first gain element. The impedance selector places an impedance in the feedback path of the first gain element or the input path of the second gain element. Errors introduced in the signal path due to the switches are attenuated by the open loop gain of the first gain element. The gain may be equally divided between both stages of the amplifier to allow for optimum band width. Optimum noise performance may be obtained by placing most of the gain in the first stage. An instrumentation amplifier may also be made which further includes a third gain element connected to the gain element with a second impedance selector in a manner similar to the connection of the first gain element to the second gain element.

摘要翻译： 包括第一和第二增益元件的可编程增益放大器通过阻抗选择器连接，该阻抗选择器允许两个增益元件的增益的可编程性。 阻抗选择器与第一增益元件的输出串联。 阻抗选择器将阻抗放置在第一增益元件的反馈路径或第二增益元件的输入路径中。 由于开关引起的信号路径中的误差由第一增益元件的开环增益衰减。 增益可以在放大器的两个级之间相等地分配，以允许最佳带宽。 通过将大部分增益置于第一阶段可获得最佳噪声性能。 还可以制造一种仪表放大器，其还包括以与第一增益元件与第二增益元件的连接相似的方式用第二阻抗选择器连接到增益元件的第三增益元件。

公开(公告)号：US09287851B2

公开(公告)日：2016-03-15

申请号：US13414487

申请日：2012-03-07

申请人： A. Martin Mallinson ,  Hu Jing Yao ,  Dustin Forman

发明人： A. Martin Mallinson ,  Hu Jing Yao ,  Dustin Forman

IPC分类号： G06F17/50 ,  H03H15/02

CPC分类号： G06F17/5009 ,  H03H15/02 ,  H03K5/15 ,  H03K5/1536

摘要： A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.

摘要翻译： 描述了一种用于设计和实现有限脉冲响应（FIR）滤波器以产生多个输出信号的方法和系统，每个输出信号具有相同的频率但与另一个输出具有不同的相移。 在具有多个输出的FIR滤波器中，确定具有阻抗值的电阻器或其他元件的值，使得每个输出具有与其它输出相同的频率响应但不同的相位。 这是通过在不改变频域响应的电阻值的时域计算中包括相位因子来实现的。 相移是恒定的，与输出信号的频率无关。

公开(公告)号：US20120246208A1

公开(公告)日：2012-09-27

申请号：US13425348

申请日：2012-03-20

申请人： A. Martin Mallinson

发明人： A. Martin Mallinson

IPC分类号： G06F17/10 ,  G06F7/523

CPC分类号： H03H17/06 ,  H03H15/00

摘要： A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

摘要翻译： 公开了一种具有差分输出且能够具有负系数的有限脉冲响应（FIR）滤波器，以及一种设计滤波器的方法。 与现有技术相比，其中两个输出信号需要使用与产生滤波器的期望响应的傅里叶系数对应的两组相同的阻抗装置，所描述的方法和系统仅使用一组阻抗装置， 因此约为现有技术中使用的阻抗装置数量的一半。 这通过适当地选择哪些电阻有助于哪个输出来实现，使得可以获得基本上相同的差分输出，如同对于每个信号使用对应于所有系数的阻抗器件一样。

公开(公告)号：US20080005215A1

公开(公告)日：2008-01-03

申请号：US11479410

申请日：2006-06-30

申请人： Andrew Martin Mallinson ,  Dustin Forman

发明人： Andrew Martin Mallinson ,  Dustin Forman

IPC分类号： G06F17/10

CPC分类号： H03F3/217 ,  H03F1/305

摘要： The invention has been described in the context of a system and method of removing artifacts from an audio signal during shutdown of the output. The system includes a means by which the average value may be found to be zero or sufficiently close to zero as determined by the resolution of the filter output and a means by which the filter average value being zero or close to zero is used to disconnect (or equivalently change impedance or power) of the device or devices rendering the PWM signal into the analog domain as may be implemented by a Class D bridge chip and disconnection means.

摘要翻译： 已经在关于输出关闭期间从音频信号中去除伪影的系统和方法的上下文中描述了本发明。 该系统包括通过滤波器输出的分辨率确定的平均值可以被发现为零或足够接近零的装置，并且使用滤波器平均值为零或接近零的装置来断开（ 或等效地改变阻抗或功率），使得将PWM信号转换成可由D类桥芯片和断开装置实现的模拟域。