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1.发明授权Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件公开(公告)号：US07541661B2
公开(公告)日：2009-06-02
申请号：US11614469
申请日：2006-12-21
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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2.发明授权Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件公开(公告)号：US07224037B2
公开(公告)日：2007-05-29
申请号：US10894019
申请日：2004-07-20
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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3.发明申请公开(公告)号：US20070096247A1
公开(公告)日：2007-05-03
申请号：US11614469
申请日：2006-12-21
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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4.发明授权Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件的制造方法公开(公告)号：US07790554B2
公开(公告)日：2010-09-07
申请号：US12432393
申请日：2009-04-29
IPC分类号： H01L21/77
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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5.发明申请公开(公告)号：US20090209078A1
公开(公告)日：2009-08-20
申请号：US12432393
申请日：2009-04-29
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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公开(公告)号：US06780717B2
公开(公告)日：2004-08-24
申请号：US09989061
申请日：2001-11-21
IPC分类号： H01L218236
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
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