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1.发明授权Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件的制造方法公开(公告)号：US07790554B2
公开(公告)日：2010-09-07
申请号：US12432393
申请日：2009-04-29
IPC分类号： H01L21/77
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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2.发明授权Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件公开(公告)号：US07541661B2
公开(公告)日：2009-06-02
申请号：US11614469
申请日：2006-12-21
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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3.发明授权Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件公开(公告)号：US07224037B2
公开(公告)日：2007-05-29
申请号：US10894019
申请日：2004-07-20
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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4.发明申请公开(公告)号：US20070096247A1
公开(公告)日：2007-05-03
申请号：US11614469
申请日：2006-12-21
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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公开(公告)号：US06780717B2
公开(公告)日：2004-08-24
申请号：US09989061
申请日：2001-11-21
IPC分类号： H01L218236
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
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公开(公告)号：US08604583B2
公开(公告)日：2013-12-10
申请号：US13438190
申请日：2012-04-03
申请人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
发明人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/0692 , H01L29/417
摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
摘要翻译： 本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。 半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区 形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域 在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。 阳极导体膜和n型阴极区彼此肖特基耦合。
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公开(公告)号：US08324706B2
公开(公告)日：2012-12-04
申请号：US12813144
申请日：2010-06-10
IPC分类号： H01L21/70
CPC分类号： H01L27/0629 , H01L21/823462 , H01L21/823857 , H01L28/20 , H01L28/40
摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
摘要翻译： 尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。 在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。 由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。
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公开(公告)号：US20070069326A1
公开(公告)日：2007-03-29
申请号：US11500381
申请日：2006-08-08
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L21/823462 , H01L21/823857 , H01L28/20 , H01L28/40
摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
摘要翻译： 尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。 在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。 由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。
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公开(公告)号：US07391083B2
公开(公告)日：2008-06-24
申请号：US11405540
申请日：2006-04-18
申请人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
发明人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
IPC分类号： H01L23/62
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823878 , H01L27/0629 , H01L28/40
摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
摘要翻译： 提供一种制造半导体集成电路器件的方法，所述半导体集成电路器件在同一衬底上具有高击穿电压MISFET和低击穿电压MISFET。 预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和 在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。 可以减少半导体集成电路器件的制造步骤的数量。
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10.发明授权公开(公告)号：US06803644B2
公开(公告)日：2004-10-12
申请号：US09768471
申请日：2001-01-25
IPC分类号： H01L29866
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11521 , H01L27/11546 , Y10S438/983
摘要： A plurality of connection holes 24 for connecting n+ type semiconductor region 20 of zener diodes (D1, D2) and wires 21 and 22 to each other are not arranged in the center of the n+ type semiconductor region 20, that is, in a region in which a p+ type semiconductor region 6 and the n+ type semiconductor region 20 form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes 24 are spaced from each other so that a pitch between the adjacent connection holes 24 is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes 24 are formed by means of dry etching.
摘要翻译： 用于将齐纳二极管（D1，D2）和导线21和22的n +型半导体区域20彼此连接的多个连接孔24不布置在n +型半导体区域20的中心， 在p +型半导体区域6和n +型半导体区域20形成结的区域中，配置在比结合深度的中心深的周边的区域。 此外，这些连接孔24彼此间隔开，使得相邻的连接孔24之间的间距大于电路的连接孔之间的最小间距，从而当各个连接孔24为 通过干蚀刻形成。
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