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公开(公告)号:US07655994B2
公开(公告)日:2010-02-02
申请号:US11259644
申请日:2005-10-26
申请人: Eduard A. Cartier , Mathew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
发明人: Eduard A. Cartier , Mathew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
IPC分类号: H01L29/94 , H01L21/326
CPC分类号: H01L29/513 , H01L21/28194 , H01L21/28238 , H01L21/823807 , H01L29/105 , H01L29/1083 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.