公开(公告)号：US06438719B1

公开(公告)日：2002-08-20

申请号：US09378457

申请日：1999-08-20

申请人： Mikael Lindberg ,  Stefan Gustafsson ,  Mats Ernkell

发明人： Mikael Lindberg ,  Stefan Gustafsson ,  Mats Ernkell

IPC分类号： G01R3128

CPC分类号： G11C29/04 ,  G11C2029/0409

摘要： A method and system for testing a memory in operation. A storage unit is used to temporarily free one memory location in the memory, making it possible to check this memory location for bit errors. Data intended for the selected memory location is stored in the storage unit, and instead a test pattern is written into the memory location to be tested and read out again, all in coordination with the normal operation of the memory. If the pattern read from the test location does not match the written test pattern, an alarm is raised.

摘要翻译： 用于测试操作中的存储器的方法和系统。 存储单元用于临时释放存储器中的一个存储器位置，使得可以检查该存储器位置以获得位错误。 用于所选择的存储器位置的数据被存储在存储单元中，而是将测试图案写入要被测试和再次读出的存储器位置，所有这些都与存储器的正常操作协调。 如果从测试位置读取的模式与写入的测试模式不匹配，则会发出警报。

公开(公告)号：US5633878A

公开(公告)日：1997-05-27

申请号：US376147

申请日：1995-01-20

申请人： Mats Ernkell ,  Stefan Sahl

发明人： Mats Ernkell ,  Stefan Sahl

IPC分类号： G06F11/22 ,  G06F5/10 ,  G06F5/12 ,  G06F11/10 ,  G11C29/00 ,  G06F11/00

CPC分类号： G06F5/10 ,  G06F11/1008 ,  G11C29/88

摘要： A self-diagnostic asynchronous data buffer includes an addressable buffer having a write address determined by a write counter and a read address determined by a read counter. A write clock controls storage into the buffer and updating of the write counter. A read clock controls reading from the buffer and updating of the read counter. The self-diagnostic asynchronous data buffer additionally has a test register, an address counter, and a state machine. To determine whether a hardware fault exists, the state machine compares the address counter output with the output of the write counter. When the two are equal, the next write to the addressable buffer causes the input data to also be stored in the test register. Next, the address counter output is compared with the output of the read counter. When the two addresses are equal, the output data from the addressable buffer is compared to the value stored in the test register. Inequality between these two values indicates a hardware fault. In an alternative embodiment, a parallel asynchronous data buffer operates by storing into a parity register a parity value of the input data, rather than the input data itself. When the address counter output is equal to the output address of the read counter, parity of the output data from the data buffer is computed and then compared with the value stored in the parity register. Inequality between these two values indicates a hardware fault.

摘要翻译： 自诊断异步数据缓冲器包括具有由写计数器确定的写入地址的可寻址缓冲器和由读取计数器确定的读取地址。 写入时钟将存储器控制到缓冲区并更新写入计数器。 读时钟控制从缓冲器的读取和读取计数器的更新。 自诊断异步数据缓冲器还具有测试寄存器，地址计数器和状态机。 为了确定是否存在硬件故障，状态机将地址计数器输出与写计数器的输出进行比较。 当两者相等时，下一次写入可寻址缓冲区会导致输入数据也存储在测试寄存器中。 接下来，将地址计数器输出与读计数器的输出进行比较。 当两个地址相等时，来自可寻址缓冲器的输出数据与存储在测试寄存器中的值进行比较。 这两个值之间的不等式表示硬件故障。 在替代实施例中，并行异步数据缓冲器通过将输入数据的奇偶校验值而不是输入数据本身存入奇偶校验寄存器来进行操作。 当地址计数器输出等于读计数器的输出地址时，计算来自数据缓冲器的输出数据的奇偶性，然后与存储在奇偶寄存器中的值进行比较。 这两个值之间的不等式表示硬件故障。