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    Partial Die Process for Uniform Etch Loading of Imprint Wafers
    1.
    发明申请
    Partial Die Process for Uniform Etch Loading of Imprint Wafers 失效
    印版晶片均匀刻蚀加工的部分模切工艺

    公开(公告)号：US20110248384A1

    公开(公告)日：2011-10-13

    申请号：US12759489

    申请日：2010-04-13

    申请人： Matt Malloy

    发明人： Matt Malloy

    IPC分类号： H01L21/306 ,  B05C11/02 ,  H01L29/00 ,  B05D5/12

    CPC分类号： H01L21/306 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/30

    摘要： Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.

    摘要翻译： 公开了在光刻工艺中由半导体芯片的部分裸片的方便处理的方法，系统和装置。 实施例利用不与部分模具进行物理接触的压印式模板进行曝光。 在一个实施例中，公开了一种具有至少一个完整管芯和至少一个部分管芯的半导体工艺。 部分地通过使用蚀刻工艺来制造半导体芯片，该蚀刻工艺利用当压印模板与被分配到至少一个完整裸片上的抗蚀剂接触时构造成暴露于至少一个全裸片的印模模板 。 此外，半导体芯片的至少一个部分裸片被配置为暴露于压印模板，而不将模板接触抗蚀剂分配到至少一个部分裸片上。

    Partial die process for uniform etch loading of imprint wafers
    2.
    发明授权
    Partial die process for uniform etch loading of imprint wafers 失效

    公开(公告)号：US08366431B2

    公开(公告)日：2013-02-05

    申请号：US12759489

    申请日：2010-04-13

    申请人： Matt Malloy

    发明人： Matt Malloy

    IPC分类号： B29C59/02

    CPC分类号： H01L21/306 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/30

    摘要： Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.