公开(公告)号：US20070224745A1

公开(公告)日：2007-09-27

申请号：US11308390

申请日：2006-03-21

Applicant: Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

Inventor： Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

IPC: H01L21/8234

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor device including a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer is disclosed. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric layer. The source/drain regions are disposed in the substrate next to the sidewalls of the gate. The stressed layer is disposed on the substrate to cover the gate and the source/drain regions.

Abstract translation: 公开了一种包括衬底，栅介质层，栅极，一对源极/漏极区域和应力层的半导体器件。 栅极电介质层设置在基板上，并且顶部区域大于其底部区域的栅极设置在栅极介电层上。 源极/漏极区域设置在邻近栅极的侧壁的衬底中。 应力层设置在基板上以覆盖栅极和源极/漏极区域。

公开(公告)号：US07589385B2

公开(公告)日：2009-09-15

申请号：US11161170

申请日：2005-07-26

Applicant: Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

Inventor： Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

IPC: H01L27/92

CPC classification number: H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

Abstract: A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.

Abstract translation: 公开了一种包括拉伸应力NMOS晶体管和PMOS晶体管的CMOS晶体管器件。 NMOS晶体管包括栅极，栅极和半导体衬底之间的栅极氧化物层，栅极侧壁上的氧化硅偏移间隔物，注入到氧化硅偏移间隔物旁边的半导体衬底中的N型轻掺杂源/漏极，N 在N型轻掺杂源极/漏极旁边注入到半导体衬底中的重掺杂源极/漏极，覆盖栅极的拉伸应力氮化硅层，N型轻掺杂源极/漏极和N型重掺杂源极/ 排水。

公开(公告)号：US20070259503A1

公开(公告)日：2007-11-08

申请号：US11777291

申请日：2007-07-13

Applicant: Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

Inventor： Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

IPC: H01L21/336

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor device is provided herein. The semiconductor device includes a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric layer. The source/drain regions are disposed in the substrate next to the sidewalls of the gate. The stressed layer is disposed on the substrate to cover the gate and the source/drain regions.

Abstract translation: 本发明提供一种制造半导体器件的方法。 半导体器件包括衬底，栅介质层，栅极，一对源/漏区和应力层。 栅极电介质层设置在基板上，并且顶部区域大于其底部区域的栅极设置在栅极介电层上。 源极/漏极区域设置在邻近栅极的侧壁的衬底中。 应力层设置在基板上以覆盖栅极和源极/漏极区域。

公开(公告)号：US20070024321A1

公开(公告)日：2007-02-01

申请号：US11161170

申请日：2005-07-26

Applicant: Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

Inventor： Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

IPC: H03K19/0175

CPC classification number: H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

Abstract: A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.

Abstract translation: 公开了一种包括拉伸应力NMOS晶体管和PMOS晶体管的CMOS晶体管器件。 NMOS晶体管包括栅极，栅极和半导体衬底之间的栅极氧化物层，栅极侧壁上的氧化硅偏移间隔物，注入到氧化硅偏移间隔物旁边的半导体衬底中的N型轻掺杂源/漏极，N 在N型轻掺杂源极/漏极旁边注入到半导体衬底中的重掺杂源极/漏极，覆盖栅极的拉伸应力氮化硅层，N型轻掺杂源极/漏极和N型重掺杂源极/ 排水。