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1.发明授权
公开(公告)号：US5987588A
公开(公告)日：1999-11-16
申请号：US143344
申请日：1998-08-28
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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2.发明授权Processor architecture providing speculative, out of order execution of instructions and trap handling 失效处理器架构提供了推测，乱序执行指令和陷阱处理
公开(公告)号：US5832293A
公开(公告)日：1998-11-03
申请号：US911756
申请日：1997-08-15
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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3.发明授权
公开(公告)号：US5708841A
公开(公告)日：1998-01-13
申请号：US710358
申请日：1996-09-17
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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公开(公告)号：US5561776A
公开(公告)日：1996-10-01
申请号：US469190
申请日：1995-06-06
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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Patent Agency Ranking5.发明授权Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code 失效处理器架构具有无序执行，推测性分支，并且优先于影响条件代码的指令
公开(公告)号：US5625837A
公开(公告)日：1997-04-29
申请号：US471651
申请日：1995-06-06
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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公开(公告)号：US5627983A
公开(公告)日：1997-05-06
申请号：US470408
申请日：1995-06-06
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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7.发明授权Processor architecture supporting multiple speculative branches and trap handling 失效处理器架构支持多个投机分支和陷阱处理
公开(公告)号：US5592636A
公开(公告)日：1997-01-07
申请号：US468785
申请日：1995-06-06
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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8.发明授权Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched 失效处理器架构具有独立地取出指令的发布和更新操作，这些指令按顺序被分配和存储
公开(公告)号：US5487156A
公开(公告)日：1996-01-23
申请号：US622893
申请日：1990-12-05
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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9.发明授权
公开(公告)号：US5797025A
公开(公告)日：1998-08-18
申请号：US749291
申请日：1996-11-14
Applicant: Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
Inventor： Valeri Popescu , Merle A. Schultz , Gary A. Gibson , John E. Spracklen , Bruce D. Lightner
CPC classification number: G06F9/3855 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
Abstract translation: 描述了使用通过动态寄存器文件与指令执行功能分离的指令获取功能来改进计算效率的处理器架构。 指令获取功能在自由运行模式下运行，如果由于数据不可用或由于其他指令依赖性而导致无法执行获取的指令，则该模式不会停止。 分支指令以预测的方向进行，并且所有指令的执行结果暂时存储在等待验证或无效之前，依赖性随后变得可用。 对于稍后无效的执行指令的分支，执行的指令的结果从临时存储器刷新，并且先前在分支开始执行的关于预测依赖性的初始指令对随后变得可用的实际数据重新执行， 并且这种分支中的所有后续指令也将基于在该分支中执行先前指令实际可获得的依赖性来重新执行。
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