公开(公告)号：US5764710A

公开(公告)日：1998-06-09

申请号：US573407

申请日：1995-12-15

申请人： Michael B. Cheng ,  Anthony Yap Wong ,  Charles Hsiao ,  Belle Wong

发明人： Michael B. Cheng ,  Anthony Yap Wong ,  Charles Hsiao ,  Belle Wong

IPC分类号： G06F1/10 ,  H04L7/02 ,  H04L7/00

CPC分类号： G06F1/10 ,  H04L7/02

摘要： A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable. Clock-enable conditioning to prevent partial output pulses is merged with the synchronizing function to further reduce latency.

摘要翻译： 具有降低延迟的同步器用于将时钟使能信号同步并调节到自由运行的时钟。 一旦时钟使能信号被同步，它被用于启用和禁用自由运行时钟门控到门控时钟，门控时钟响应于时钟使能信号暂停脉冲。 第一级触发器是“元稳定的硬化”，以降低其成为元稳定的概率。 时钟门控和清晰输入可以降低同时输入将触发触发器的时序，从而导致亚稳态的机会。 产生清除脉冲以清除触发器。 清除脉冲使触发器更倾向于比异步输入的一个边缘变得亚稳态。 然后调整到第二级触发器的稳定时间，以解决亚稳态的这种偏差。 对于更可能变得亚稳的边缘，第二阶段的建立时间增加。 用于防止部分输出脉冲的时钟使能调节与同步功能合并，以进一步减少延迟。

公开(公告)号：US5694072A

公开(公告)日：1997-12-02

申请号：US520028

申请日：1995-08-28

申请人： Charles Hsiao ,  Michael B. Cheng ,  David Kwong

发明人： Charles Hsiao ,  Michael B. Cheng ,  David Kwong

IPC分类号： G05F3/20 ,  G05F1/10

CPC分类号： G05F3/205

摘要： A substrate bias generator for an integrated circuit has a charge pump driven by an oscillator. The oscillator is enabled and disabled to save power and control the voltage-level itself for the substrate bias. An enabling circuit senses the substrate voltage and enables the oscillator when the substrate voltage rises above a bias set by a programmable reference voltage. The enabling circuit which senses the voltage on the substrate draws no active current from the substrate. The sensing circuit includes a transistor with only its bulk terminal connected to the substrate; the source, gate, and drain of this sensing transistor are not connected to the substrate. A differential comparator compares the output of the sensing transistor to the programmable reference voltage and enables the oscillator when the sensing transistor output is lower than the reference voltage. The sensing transistor attenuates large swings in the substrate voltage to provide the differential comparator with a small voltage swing which keeps the differential comparator operating near its optimum design point. Since no active current is drawn from the substrate when sensing the substrate voltage, no IR voltage drops can develop from the enabling and sensing circuit. Thus latch-up immunity is improved and substrate noise is reduced.

摘要翻译： 用于集成电路的衬底偏置发生器具有由振荡器驱动的电荷泵。 振荡器被使能和禁止，以节省功率并控制电压电平本身为衬底偏置。 启动电路感测衬底电压，并且当衬底电压上升到由可编程参考电压设置的偏置之上时使能振荡器。 感测衬底上的电压的使能电路从衬底上没有吸收有效电流。 感测电路包括仅具有其主体端子连接到衬底的晶体管; 该感测晶体管的源极，栅极和漏极不连接到衬底。 差分比较器将感测晶体管的输出与可编程参考电压进行比较，并在感测晶体管输出低于参考电压时使能振荡器。 感测晶体管衰减衬底电压中的大摆幅，为差分比较器提供小的电压摆幅，使差分比较器工作在其最佳设计点附近。 由于在感测衬底电压时没有从衬底吸取有效电流，所以不能从使能和感测电路产生IR电压降。 从而提高了闩锁抗扰性，降低了衬底噪声。