公开(公告)号：US06748039B1

公开(公告)日：2004-06-08

申请号：US09637710

申请日：2000-08-11

申请人： Michael E. Bates

发明人： Michael E. Bates

IPC分类号： H04L700

CPC分类号： G06F5/10 ,  H04L7/005

摘要： A system and method for synchronizing the skip pattern to two clock domains and initializing the clock skipping buffer which enables data transfers between the two clock domains. In one embodiment, a circuit comprises a pair of alignment detection units, a synchronous reset unit, a skip pattern generator, a counter reset unit and a data transfer buffer. Each of the alignment units is configured to detect the alignment of the clock signal in one of the clock domains with a reference clock signal and generate a signal indicative of the alignment. This signal is conveyed to the synchronous reset unit and the counter reset unit. The alignment signal generated by one alignment unit is also conveyed to the skip pattern generator. The synchronous reset unit accepts the alignment signals from the alignment units and generates concurrent reset signals (i.e., one for each of the two clock domains) to initialize the counter reset unit. The counter reset unit controls the load and unload counters which control the flow data through the data transfer buffer. After the synchronous reset signals generated by the synchronization reset unit are received, the counter reset unit begins generating load and unload pulses corresponding to the respective clock domains and transmitting these signals to the data transfer buffer.

摘要翻译： 一种用于将跳过模式同步到两个时钟域并初始化时钟跳过缓冲器的系统和方法，其实现两个时钟域之间的数据传输。 在一个实施例中，电路包括一对对准检测单元，同步复位单元，跳过图案发生器，计数器复位单元和数据传输缓冲器。 每个对准单元被配置为利用参考时钟信号检测时钟信号之一中的时钟信号的对准，并产生指示对准的信号。 该信号被传送到同步复位单元和计数器复位单元。 由一个对准单元产生的对准信号也被传送到跳过图案发生器。 同步复位单元接受来自对准单元的对准信号，并且产生并发复位信号（即，对于两个时钟域中的每一个为一个）来初始化计数器复位单元。 计数器复位单元控制通过数据传输缓冲器控制流量数据的装载和卸载计数器。 在接收到由同步复位单元产生的同步复位信号之后，计数器复位单元开始产生与各个时钟域对应的负载和卸载脉冲，并将这些信号发送到数据传输缓冲器。

公开(公告)号：US06711696B1

公开(公告)日：2004-03-23

申请号：US09637985

申请日：2000-08-11

申请人： Michael E. Bates ,  Brian D. McMinn

发明人： Michael E. Bates ,  Brian D. McMinn

IPC分类号： G06F112

CPC分类号： G06F5/14 ,  G06F1/12 ,  H04L7/0012

摘要： A method and related system for transferring data between systems having different clock domains. A skip signal generation circuit calculates substantially simultaneously with the transfer of data which signals of the faster clock domain should be skipped to ensure proper operation. The skip signal generation circuit makes this determination using values representing the faster and slower frequencies of each clock domain. These values are obtained either from preset values integrated in some form onto the microprocessor substrate, or may be written to the microprocessor by external circuitry and software. The skip signal generation circuit is capable of calculating skip patterns for any ratio of faster to slower frequency and is not constrained to have integer or half-integer ratios of the faster and slower clock domains.

摘要翻译： 一种用于在具有不同时钟域的系统之间传送数据的方法和相关系统。 跳跃信号生成电路基本上与数据的传送同时计算应该跳过较快时钟域的信号以确保正确的操作。 跳过信号生成电路使用表示每个时钟域的更快和更慢频率的值进行该确定。 这些值可以从以某种形式集成到微处理器基板上的预设值获得，或者可以通过外部电路和软件写入微处理器。 跳过信号产生电路能够计算出快速到慢速频率的任何比率的跳跃模式，并且不被限制为具有较快和较慢时钟域的整数或半整数比。