中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.039 seconds)

    Packaged stacked semiconductor die and method of preparing same
    2.
    发明授权
    Packaged stacked semiconductor die and method of preparing same 有权
    封装堆叠半导体管芯及其制备方法

    公开(公告)号：US06894380B2

    公开(公告)日：2005-05-17

    申请号：US10230005

    申请日：2002-08-28

    Applicant: Tongbi Jiang ,  Michael E. Connell

    Inventor： Tongbi Jiang ,  Michael E. Connell

    IPC: H01L21/58 ,  H01L21/68 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L23/02

    CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00014

    Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto. In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area.

    Abstract translation: 描述了一种封装半导体器件的方法。 在一个实施例中，该方法包括提供晶片安装带的一部分，向晶片安装带施加粘合剂层，拉伸晶片安装带和粘合剂层，将晶片连接到拉伸的粘合剂层，切割晶片和粘合剂 将晶片切割成多个模具，并固化晶片安装带。 在另外的实施例中，该方法包括从晶片安装带去除多个管芯中的至少一个，所述移除的管芯具有与其连接的粘合层的一部分，提供具有多个与其连接的引线接合的管芯， 将去除的芯片上的粘合剂层连接到具有与其结合的引线键合的管芯。 在另一方面，本发明涉及多个层叠的半导体器件，其包括第一裸片，第一裸片具有上表面，第二裸片位于第一裸片上，第二片具有底表面，以及粘合剂 层，其定位在第一模具和第二模具中的每一个之间并且耦合到第一模具和第二模具中，粘合剂层由第一和第二表面组成，粘合剂层的第一表面耦合到第二模具的底表面，从而限定第一接触区域， 粘合剂层的第二表面耦合到第一模具的上表面，从而限定第二接触区域，第二接触区域小于第一接触区域。

    Packaged stacked semiconductor die and method of preparing same
    3.
    发明授权
    Packaged stacked semiconductor die and method of preparing same 有权
    封装堆叠半导体管芯及其制备方法

    公开(公告)号：US06514795B1

    公开(公告)日：2003-02-04

    申请号：US09974192

    申请日：2001-10-10

    Applicant: Tongbi Jiang ,  Michael E. Connell

    Inventor： Tongbi Jiang ,  Michael E. Connell

    IPC: H01L2144

    CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00014

    Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto. In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area.

    Abstract translation: 描述了一种封装半导体器件的方法。 在一个实施例中，该方法包括提供晶片安装带的一部分，向晶片安装带施加粘合剂层，拉伸晶片安装带和粘合剂层，将晶片连接到拉伸的粘合剂层，切割晶片和粘合剂 将晶片切割成多个模具，并固化晶片安装带。 在另外的实施例中，该方法包括从晶片安装带去除多个管芯中的至少一个，所述移除的管芯具有与其连接的粘合层的一部分，提供具有多个与其连接的引线接合的管芯， 将去除的芯片上的粘合剂层连接到具有与其结合的引线键合的管芯。 在另一方面，本发明涉及多个层叠的半导体器件，其包括第一裸片，第一裸片具有上表面，第二裸片位于第一裸片上，第二片具有底表面，以及粘合剂 层，其定位在第一模具和第二模具中的每一个之间并且耦合到第一模具和第二模具中，粘合剂层由第一和第二表面组成，粘合剂层的第一表面耦合到第二模具的底表面，从而限定第一接触区域， 粘合剂层的第二表面耦合到第一模具的上表面，从而限定第二接触区域，第二接触区域小于第一接触区域。

    Apparatuses for forming thin microelectronic dies
    5.
    发明授权
    Apparatuses for forming thin microelectronic dies 失效
    用于形成薄微电子管芯的装置

    公开(公告)号：US06882036B2

    公开(公告)日：2005-04-19

    申请号：US10835369

    申请日：2004-04-29

    Applicant: Nathan R. Draney ,  Michael E. Connell

    Inventor： Nathan R. Draney ,  Michael E. Connell

    IPC: H01L21/58 ,  H01L21/68 ,  H01L21/78 ,  H01L23/31 ,  H01L23/02

    CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: Methods and apparatuses for forming thin microelectronic dies. A method in accordance with one embodiment of the invention includes releasably attaching a microelectronic substrate to a support member with an attachment device. The microelectronic substrate can have a first surface, a second surface facing opposite from the first surface, and a first thickness between the first and second surfaces. The attachment device can have a releasable bond with the microelectronic substrate, wherein the bond has a bond strength that is reduced upon exposure to at least one energy. The support member can be at least partially transmissive to the at least one energy. The method can further include reducing a thickness of the microelectronic substrate and directing a quantity of the at least one energy through the support member to the attachment device to reduce the strength of the bond between the attachment device and the microelectronic substrate. At least a portion of the microelectronic substrate can then be separated from the support member. The support member can accordingly provide releasable support to the microelectronic substrate while the thickness of the microelectronic substrate is reduced.

    Abstract translation: 用于形成薄微电子管芯的方法和装置。 根据本发明的一个实施例的方法包括利用附接装置将微电子衬底可释放地附接到支撑构件。 微电子衬底可以具有第一表面，与第一表面相对的第二表面和第一和第二表面之间的第一厚度。 附接装置可以具有与微电子衬底的可释放的结合，其中所述键具有在暴露于至少一种能量时降低的粘合强度。 支撑构件可以至少部分地透射至少一种能量。 该方法还可以包括减小微电子衬底的厚度并将一定量的至少一种能量通过支撑构件引导到附接装置，以降低附着装置和微电子衬底之间的结合强度。 然后可以将微电子衬底的至少一部分与支撑构件分离。 因此，支撑构件可以在微电子衬底的厚度减小的同时为微电子衬底提供可释放的支撑。

    Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
    6.
    发明授权
    Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive 有权
    晶圆背面涂层以平衡来自晶片前面钝化层的应力，并用作芯片附着粘合剂

    公开(公告)号：US07727785B2

    公开(公告)日：2010-06-01

    申请号：US11269069

    申请日：2005-11-07

    Applicant: Michael E. Connell ,  Tongbi Jiang

    Inventor： Michael E. Connell ,  Tongbi Jiang

    IPC: H01L21/00

    CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L2224/94 ,  H01L2224/03

    Abstract: A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to an opposite side from a stress-causing layer before the semiconductor die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.

    Abstract translation: 在半导体管芯，晶片或类似衬底中平衡层引起的压缩或拉伸应力的方法在半导体管芯或晶片显着翘曲之前使用附着在与应力引起层相反的一侧的应力平衡层（SBL） 被提供。 SBL还可以用作或支撑用于管芯附着的粘合剂层，并且是用于增强标记方法的可标记材料。

    Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
    8.
    发明授权
    Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive 有权
    晶圆背面涂层以平衡来自晶片前面钝化层的应力，并用作芯片附着粘合剂

    公开(公告)号：US07169685B2

    公开(公告)日：2007-01-30

    申请号：US10082372

    申请日：2002-02-25

    Applicant: Michael E. Connell ,  Tongbi Jiang

    Inventor： Michael E. Connell ,  Tongbi Jiang

    IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78

    CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L2224/94 ,  H01L2224/03

    Abstract: A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach, and be of a markable material for an enhance marking method.

    Abstract translation: 在半导体管芯，晶片或类似衬底中平衡层引起的压缩或拉伸应力的方法使用在晶粒或晶片显着翘曲之前附着在与应力引起层相反的一侧的应力平衡层（SBL） 提供。 SBL还可以用作或支撑用于管芯附着的粘合剂层，并且是用于增强标记方法的可标记材料。

Patent Agency Ranking