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    Low cost and high RAS mirrored memory
    1.
    发明授权
    Low cost and high RAS mirrored memory 失效
    低成本和高RAS镜像记忆

    公开(公告)号：US06766429B1

    公开(公告)日：2004-07-20

    申请号：US09652752

    申请日：2000-08-31

    申请人： Patrick Maurice Bland ,  Thomas Basil Smith, III ,  Robert Brett Tremaine ,  Michael Edward Wazlowski

    发明人： Patrick Maurice Bland ,  Thomas Basil Smith, III ,  Robert Brett Tremaine ,  Michael Edward Wazlowski

    IPC分类号： G06F1200

    CPC分类号： G06F11/1666 ,  G06F11/20 ,  G06F12/023 ,  G06F12/0292 ,  G06F2212/401

    摘要： An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.

    摘要翻译： 具有存储器压缩的数据处理系统的结构，方法和装置以及形成单个统一存储器的两个公共存储器或能够在存在硬件故障或冗余“双工”计算机维护中断时能够连续操作的双存储器系统， 而不需要复制存储器件的成本。 存储器控制器采用硬件存储器压缩以将存储器需求减少一半，这补偿了冗余存储器所需的存储器的倍增。 存储器控制器采用错误检测和校正码，用于在读取访问期间检测存储子系统故障。 在检测到故障时，硬件自动将读访问重新发送到逻辑上与故障库相同的单独的存储体。 在存储器被识别为故障之后，存储器控制器排除对存储体的进一步读取访问，允许更换而不中断应用程序或操作系统软件操作。

    System and method for maintaining cache coherency using path directories
    2.
    发明授权
    System and method for maintaining cache coherency using path directories 失效
    使用路径目录维护高速缓存一致性的系统和方法

    公开(公告)号：US5900015A

    公开(公告)日：1999-05-04

    申请号：US694894

    申请日：1996-08-09

    申请人： Lorraine Maria Paola Herger ,  Kwok-Ken Mak ,  Kenneth Blair Ocheltree ,  Tu-Chih Tsai ,  Michael Edward Wazlowski

    发明人： Lorraine Maria Paola Herger ,  Kwok-Ken Mak ,  Kenneth Blair Ocheltree ,  Tu-Chih Tsai ,  Michael Edward Wazlowski

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0824 ,  G06F12/0813

    摘要： A method of maintaining cache coherency in a computer system including two or more processors sharing information, the processors coupled by two or more interconnects to a memory such that the processors are not directly coupled to the same is disclosed interconnect is disclosed. The method of maintaining cache coherency includes the steps of: accessing and sharing, by a first processor and a second processor, information from the memory and setting path indicators in directories associated with at least two of the interconnects on a respective first and second access path to the memory, and storing the information in respective associated first and second caches; and writing a new value to the information, by a writing processor sharing the information, the writing step including the steps of: invalidating other copies of the information via the path indicators; acquiring exclusive access to the information by changing the path indicators to an exclusive state; and writing the new value to the information, in response to the acquiring step.

    摘要翻译： 公开了一种在包括共享信息的两个或多个处理器共享信息的计算机系统中维持高速缓存一致性的方法，将两个或多个互连器耦合到存储器，使得处理器不直接耦合到存储器的处理器。 维护高速缓存一致性的方法包括以下步骤：由第一处理器和第二处理器访问和共享来自存储器的信息，并且在相应的第一和第二访问路径上与至少两个互连相关联的目录中设置路径指示符 并将信息存储在相关联的第一和第二高速缓存中; 并且通过共享所述信息的写入处理器向所述信息写入新的值，所述写入步骤包括以下步骤：通过所述路径指示器使所述信息的其他副本无效; 通过将路径指示器更改为独占状态来获取对信息的独占访问; 并且响应于获取步骤将新的值写入信息。

    Low cost and high RAS mirrored memory
    4.
    发明授权
    Low cost and high RAS mirrored memory 失效
    低成本和高RAS镜像记忆

    公开(公告)号：US07287138B2

    公开(公告)日：2007-10-23

    申请号：US10859826

    申请日：2004-06-03

    申请人： Patrick Maurice Bland ,  Thomas Basil Smith, III ,  Robert Brett Tremaine ,  Michael Edward Wazlowski

    发明人： Patrick Maurice Bland ,  Thomas Basil Smith, III ,  Robert Brett Tremaine ,  Michael Edward Wazlowski

    IPC分类号： G06F12/00

    CPC分类号： G06F11/1666 ,  G06F11/20 ,  G06F12/023 ,  G06F12/0292 ,  G06F2212/401

    摘要： An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.

    摘要翻译： 具有存储器压缩的数据处理系统的结构，方法和装置以及形成单个统一存储器的两个公共存储器或能够在存在硬件故障或冗余“双工”计算机维护中断时能够连续操作的双存储器系统， 而不需要复制存储器件的成本。 存储器控制器采用硬件存储器压缩以将存储器需求减少一半，这补偿了冗余存储器所需的存储器的倍增。 存储器控制器采用错误检测和校正码，用于在读取访问期间检测存储子系统故障。 在检测到故障时，硬件自动将读访问重新发送到逻辑上与故障库相同的单独的存储体。 在存储器被识别为故障之后，存储器控制器排除对存储体的进一步读取访问，允许更换而不中断应用程序或操作系统软件操作。