公开(公告)号：US5860014A

公开(公告)日：1999-01-12

申请号：US729307

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3861

摘要： A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.

摘要翻译： 一种用于维护使用寄存器处理指令的处理器的寄存器的内容的方法和装置。 条目存储在缓冲器中，用于通过可中断指令中断来恢复寄存器内容。 条目包括用于减少为恢复选择的条目数量的信息。 响应于中断和信息来选择一组缓冲器条目用于恢复寄存器内容。 该集合仅包括为了响应于中断而恢复内容所必需的条目，使得处理器寄存器的内容可以在单个处理器周期中被恢复，即使对于第一个寄存器和多个条目存储了多个条目 存储在第二个寄存器中。

公开(公告)号：US5784604A

公开(公告)日：1998-07-21

申请号：US959183

申请日：1992-10-09

申请人： John Stephen Muhich ,  Terrence Matthew Potter ,  Steven Wayne White

发明人： John Stephen Muhich ,  Terrence Matthew Potter ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3804

摘要： A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies an associated conditional branch to be taken in response to a selected outcome of processing one or more sequential instructions. Upon detection of a conditional branch instruction within the queue, a group of target instructions are fetched based upon a prediction that an associated conditional branch will be taken. Sequential instructions within the queue following the conditional branch instruction are then purged and the target instructions loaded into the queue only in response to a successful a retrieval of the target instructions, such that the sequential instructions may be processed without delay if the prediction that the conditional branch is taken proves invalid prior to retrieval of the target instructions. Alternately, the purged sequential instructions may be refetched after loading the target instructions such that the sequential instructions may be executed with minimal delay if the prediction that the conditional branch is taken proves invalid after loading the target instructions. In yet another embodiment, the sequential instructions within the queue following the conditional branch instruction are purged only in response to a successful retrieval of the target instructions and an imminent execution of the conditional branch instruction.

摘要翻译： 公开了一种用于在流水线处理器系统中的条件分支指令执行期间减少运行时间延迟的方法和系统。 处理一系列排队的顺序指令和条件分支指令，其中每个条件分支指令响应于处理一个或多个顺序指令的所选结果来指定要采取的相关联的条件分支。 在检测到队列内的条件分支指令之后，基于将采用相关联的条件分支的预测来取得一组目标指令。 随后条件分支指令之后的队列中的顺序指令被清除，并且目标指令仅仅响应于目标指令的成功检索而被加载到队列中，使得如果预测条件 在检索目标指令之前，分支被认为是无效的。 或者，可以在加载目标指令之后重新抽取清除的顺序指令，使得如果在加载目标指令之后条件分支的预测被证明是无效的，则可以以最小延迟执行顺序指令。 在另一个实施例中，仅在响应于目标指令的成功检索和条件分支指令的即将执行之后才清除在条件分支指令之后的队列内的顺序指令。

公开(公告)号：US08195879B2

公开(公告)日：2012-06-05

申请号：US12437624

申请日：2009-05-08

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US07530063B2

公开(公告)日：2009-05-05

申请号：US10855729

申请日：2004-05-27

申请人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoqing Gao ,  John David McCalpin ,  Francis Patrick O'Connell ,  Pascal Vezolle ,  Steven Wayne White

发明人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoqing Gao ,  John David McCalpin ,  Francis Patrick O'Connell ,  Pascal Vezolle ,  Steven Wayne White

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.

摘要翻译： 提供了修改形成循环的指令的方法和系统。 修改形成循环的指令的方法包括修改形成循环的指令，包括：确定指令的静态和动态特性; 基于在正在处理所述指令的处理器中形成高速缓存的单独的等效部分的数量来选择所述指令的修改因子; 以及当指令满足基于静态和动态特性的修改标准时，修改指令以根据修改因子和静态和动态特性来交织循环中的指令。

公开(公告)号：US06266767B1

公开(公告)日：2001-07-24

申请号：US09296871

申请日：1999-04-22

申请人： Kurt Alan Feiste ,  John Stephen Muhich ,  Steven Wayne White

发明人： Kurt Alan Feiste ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9312

CPC分类号： G06F9/3855 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842

摘要： A processor (100) includes a preload queue (160) for storing a plurality of preload entries. Each preload entry is associated with a preload instruction and includes the address and byte count defined by the respective preload and an identifier associated with the respective preload. A comparison unit (170) associated with the preload queue (160) identifies each conflicting preload entry, that is, each preload entry associated with a preload instruction that conflicts with an older store instruction. The oldest preload instruction associated with one of the conflicting preload entries represents a target preload. The processor (100) may flush this target preload along with all instructions executed after the target preload in order to correct for the conflict between the target preload and store instruction.

摘要翻译： 处理器（100）包括用于存储多个预加载条目的预加载队列（160）。 每个预加载条目与预加载指令相关联，并且包括由相应的预载荷定义的地址和字节计数以及与相应的预载荷相关联的标识符。 与预加载队列（160）相关联的比较单元（170）识别每个冲突的预加载条目，即与与旧存储指令冲突的预加载指令相关联的每个预加载条目。 与其中一个冲突的预加载条目相关联的最早的预加载指令表示目标预加载。 处理器（100）可以与目标预加载之后执行的所有指令一起刷新该目标预载荷，以便校正目标预加载和存储指令之间的冲突。

公开(公告)号：US6098167A

公开(公告)日：2000-08-01

申请号：US829667

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3863

摘要： In maintaining the state of a processor, a dispatched instruction is given an identification tag and an associated entry in an architectural register table. The identification tag of the dispatched instruction is written to the entry in the architectural register table, if the identification tag of the dispatched instruction is more recent than a prior instruction identification tag stored in the entry.

摘要翻译： 在维护处理器的状态时，在架构寄存器表中给出分派指令的识别标签和相关联的条目。 如果调度指令的识别标签比存储在条目中的先前指令标识标签更新，则将调度指令的识别标签写入架构寄存器表中的条目。

公开(公告)号：US6070238A

公开(公告)日：2000-05-30

申请号：US927889

申请日：1997-09-11

申请人： Kurt Alan Feiste ,  John Stephen Muhich ,  Steven Wayne White

发明人： Kurt Alan Feiste ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F11/28

CPC分类号： G06F9/30043 ,  G06F11/28 ,  G06F9/3816 ,  G06F9/3834

摘要： One aspect of the invention relates to a super scalar processor having a memory which as addressable with respect to the combination of a page address and a page offset address, and provides a method for detecting an overlap condition between a present instruction and a previously executed instruction, the previously executed instruction being executed prior to execution of the present instruction. In one embodiment, the method comprises the steps of dividing the present instruction into a plurality of aligned memory accesses; determining the page offset for at least one of the aligned accesses; and comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction.

摘要翻译： 本发明的一个方面涉及一种具有存储器的超标量处理器，该存储器相对于页地址和页偏移地址的组合可寻址，并且提供了一种用于检测当前指令和先前执行的指令之间的重叠条件的方法 ，在执行本指令之前执行的先前执行的指令。 在一个实施例中，该方法包括以下步骤：将本指令划分成多个对齐的存储器存取; 确定对齐的访问中的至少一个的页偏移; 并将本指令的页偏移量和字节计数与先前执行的指令的页偏移量和字节数进行比较。

公开(公告)号：US6021467A

公开(公告)日：2000-02-01

申请号：US713056

申请日：1996-09-12

申请人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F12/0859 ,  G06F12/0897 ,  Y02B60/1225

摘要： An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.

摘要翻译： 一种用于处理信息处理系统中的多个高速缓存未命中到单个高速缓存行的装置和方法，该信息处理系统包括用于存储不在一级高速缓存中的数据的请求的未命中队列，以及比较器，用于将存储在所述未命中队列中的数据的请求与 确定是否存在针对二级缓存的同一高速缓存行中的数据的多个请求。 来自与二级缓存相同的高速缓存行的数据的新请求作为旧队列中的数据的较早原始请求被标记为加载命中重新加载。 标记为加载命中重载的请求随后与匹配的原始请求分组在一起并一起转发到二级缓存，其中原始请求请求来自二级缓存的数据。 加载命中重新加载请求不访问二级缓存，而是通过从匹配的原始请求的二级缓存输出的高速缓存行中提取数据来绕过二级缓存的访问。 本发明减少对二级高速缓存的访问次数，并且允许当发生多个连续一级高速缓存未命中时并行地对数据请求进行满足。

公开(公告)号：US5913048A

公开(公告)日：1999-06-15

申请号：US829663

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of assigning an identification tag to an instruction, and dispatching the instruction, the identification tag and source information to an execution queue.

摘要翻译： 本发明涉及一种在处理器中发出指令的方法。 在本发明的一个版本中，该方法包括以下步骤：向指令分配识别标签，并将指令，识别标签和源信息分派到执行队列。

公开(公告)号：US5887161A

公开(公告)日：1999-03-23

申请号：US829662

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.

摘要翻译： 本发明涉及一种在处理器中发出指令的方法。 在本发明的一个版本中，该方法包括以下步骤：将指令和源信息发送到队列，确定源信息的有效性，以及响应源信息有效性发出执行指令。