公开(公告)号：US07158396B2

公开(公告)日：2007-01-02

申请号：US10723833

申请日：2003-11-26

申请人： Noel Hatsch ,  Winfried Kamp ,  Siegmar Köppe ,  Thomas Künemund ,  Heinz Söldner ,  Michel D'Argouges

发明人： Noel Hatsch ,  Winfried Kamp ,  Siegmar Köppe ,  Thomas Künemund ,  Heinz Söldner ,  Michel D'Argouges

IPC分类号： G11C15/00

CPC分类号： G06F7/02 ,  G06F2207/025 ,  G11C15/04

摘要： The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one storage node (12; 13) for storing a first bit of a data word; a second memory device (11) with a word line input (WL) and at least one storage node (14; 15) for storing a second bit of a data word; and a comparator device (16) for comparing the first and second stored bits with two precoded comparison bits fed via four inputs (20; 21; 22; 23) and for driving a hit node (17) in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.

摘要翻译： 本发明提供一种CAM（内容可寻址存储器）装置，其具有：具有字线输入（WL）的第一存储器件（10）和用于存储数据字的第一位的至少一个存储节点（12; 13） 具有字线输入（WL）的第二存储器件（11）和用于存储数据字的第二位的至少一个存储节点（14; 15） 以及比较器装置（16），用于将第一和第二存储位与经由四个输入（20; 21; 22; 23）馈送的两个预编码比较位进行比较，并且用于在第一个存储位的情况下驱动命中节点（17） 对应于对应于第二比较位的第一比较位和第二存储位。

公开(公告)号：US08854866B2

公开(公告)日：2014-10-07

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

IPC分类号： G11C11/00 ,  G06F21/72 ,  H04L9/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

公开(公告)号：US20120020145A1

公开(公告)日：2012-01-26

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

IPC分类号： G11C11/40 ,  G11C8/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。