公开(公告)号：US5481484A

公开(公告)日：1996-01-02

申请号：US953533

申请日：1992-09-28

申请人： Munehiro Ogawa, deceased ,  Masato Iwabuchi ,  Hitoshi Sugihara ,  Saburo Hojo ,  Masami Kinoshita ,  Osamu Yamashiro ,  Goichi Yokomizo ,  Mikako Miyama

发明人： Munehiro Ogawa, deceased ,  Masato Iwabuchi ,  Hitoshi Sugihara ,  Saburo Hojo ,  Masami Kinoshita ,  Osamu Yamashiro ,  Goichi Yokomizo ,  Mikako Miyama

IPC分类号： G06F11/25 ,  G01R31/3167 ,  G06F17/50 ,  G06J1/00

CPC分类号： G06F17/5022 ,  G01R31/3167 ,  G06F17/5036

摘要： A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.

摘要翻译： 考虑到对模拟分析电路部分的影响，提供混合模式模拟方法和装置，用于高精度地模拟数字分析电路部分和模拟分析电路部分的总体特性，它们都经过混合模式模拟 由数字分析电路部分消耗的电流。 更具体地，与逻辑模拟同步地确定由模拟分析电路部分提供由于由逻辑模拟实现的数字分析电路部分的操作状态而产生的电流的电流计算的等效电路的电流值，并且 由此得到的电流计算的等效电路由模拟分析电路部分组成，该复合电路进行电路仿真。

公开(公告)号：US5416717A

公开(公告)日：1995-05-16

申请号：US577434

申请日：1990-09-04

申请人： Mikako Miyama ,  Goichi Yokomizo ,  Chikako Yoshida

发明人： Mikako Miyama ,  Goichi Yokomizo ,  Chikako Yoshida

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5081

摘要： In verifying an LSI layout pattern, the whole layout pattern is converted into circuit data and a subcircuit to be verified is picked up and subjected to simulation. After converting the layout pattern into the transistor level circuit data, the transistor level circuit data is transformed into a logic gate level circuit data while judging a clocked gate included in the subcircuit. After picking up a subcircuit in a predetermined manner, an approximate load is connected to the interface port of the picked-up subcircuit.

摘要翻译： 在验证LSI布局图案时，整个布局图案被转换成电路数据，并且要检验的子电路被拾取并进行仿真。 在将布局图案转换为晶体管电平电路数据之后，晶体管电平电路数据被转换为逻辑门电平电路数据，同时判断包括在子电路中的时钟门。 在以预定方式拾取子电路之后，将近似负载连接到所拾取的子电路的接口端口。