公开(公告)号：US5796282A

公开(公告)日：1998-08-18

申请号：US700613

申请日：1996-08-12

申请人： Milo David Sprague ,  Robert J. Murray

发明人： Milo David Sprague ,  Robert J. Murray

IPC分类号： H03K19/096 ,  H03K19/017

CPC分类号： H03K19/0963

摘要： The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.

摘要翻译： 本发明提供了一种用于高速多米诺逻辑管道的锁定机构。 锁定机构允许跨锁存器边界的时间借用，为下一级感测输出提供足够的保持时间，并提供一种电路配置，其中与锁存机构相关的竞态条件具有固有的正裕量。 本发明的锁定机构适用于全自动复位多米诺逻辑，全局复位多米诺逻辑或其任何组合。 锁定机构是一个集主导锁存器，其设置输入由管道中最后一个多米诺逻辑门的输出驱动，并且其复位输入由分支管理中最后一个多米诺逻辑门的输出驱动，与延迟版 脉冲时钟触发了管道的多米诺骨链。

公开(公告)号：US5828234A

公开(公告)日：1998-10-27

申请号：US702244

申请日：1996-08-27

申请人： Milo David Sprague

发明人： Milo David Sprague

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： The pulsed reset single phase dynamic logic of the present invention reorders the conventional modes of operation such that in a single cycle of operation of a domino logic circuit, reset occurs first, followed sequentially by gap2, evaluation and gap1. To reset each domino stage prior to evaluating, a reset pulse is propagated to each domino stage, with an evaluate signal arriving at each stage as the reset pulse is ending. The circuit configuration of the present invention creates a different, but shorter and easier to manage set of race conditions. The present invention permits the creation of faster and more robust circuit designs.

摘要翻译： 本发明的脉冲复位单相动态逻辑重新排列常规操作模式，使得在多米诺逻辑电路的单个操作周期中，首先进行复位，随后依次为gap2，评估和gap1。 为了在评估之前复位每个多米诺骨牌阶段，复位脉冲被传播到每个多米诺骨牌阶段，当复位脉冲结束时，评估信号到达每个阶段。 本发明的电路结构创建了不同的但更短且更容易管理的竞赛条件。 本发明允许创建更快和更坚固的电路设计。