公开(公告)号：US08405168B2

公开(公告)日：2013-03-26

申请号：US13017777

申请日：2011-01-31

Applicant: Chia-Yi Lin ,  Min-Cheng Chen ,  Hou-Yu Chen

Inventor： Chia-Yi Lin ,  Min-Cheng Chen ,  Hou-Yu Chen

IPC: H01L29/78

CPC classification number: B82Y40/00 ,  B82Y10/00 ,  H01L29/0676

Abstract: The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion.

Abstract translation: 本发明公开了一种纳米线制造方法和使用由其制造的纳米线的半导体元件。 本发明的方法包括以下步骤：提供基底; 在基板上依次沉积二氧化硅层和氮化硅层; 在所述氮化硅层上形成图案化的光致抗蚀剂层; 使用图案化的光致抗蚀剂层作为掩模来蚀刻氮化硅层和二氧化硅层，其中衬底被部分蚀刻掉以形成突起; 去除图案化的光致抗蚀剂层以形成隔离层; 去除氮化硅和二氧化硅层，依次沉积介电层和多晶硅层; 并且各向异性地蚀刻多晶硅层以在介电层的位于突起的侧壁周围的区域上形成纳米线。

公开(公告)号：US20130161755A1

公开(公告)日：2013-06-27

申请号：US13451390

申请日：2012-04-19

Applicant: Min-Cheng Chen ,  Chang-Hsien Lin ,  Chia-Yi Lin ,  Tung-Yen Lai ,  Chia-Hua Ho

Inventor： Min-Cheng Chen ,  Chang-Hsien Lin ,  Chia-Yi Lin ,  Tung-Yen Lai ,  Chia-Hua Ho

IPC: H01L27/092 ,  H01L21/336 ,  B82Y99/00

CPC classification number: H01L21/84 ,  B82Y10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/78696

Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

Abstract translation: 薄膜晶体管包括半导体板，电介质层，半导体膜层，导电层，源极和漏极。 半导体面板包括基底，介质内介质层，至少一个金属线层和至少一个通孔层。 电介质层堆叠在半导体面板上。 半导体膜层层叠在电介质层上。 导电层形成在半导体膜层上。 源极形成在与通孔相邻并连接到通孔的通孔的通孔上。 漏极形成在邻近并连接到栅极通孔的通孔的另一个通孔上。 还公开了一种具有金属栅极和纳米线的薄膜晶体管的制造方法。

公开(公告)号：US20120146161A1

公开(公告)日：2012-06-14

申请号：US13017777

申请日：2011-01-31

Applicant: Chia-Yi LIN ,  Min-Cheng Chen ,  Hou-Yu Chen

Inventor： Chia-Yi LIN ,  Min-Cheng Chen ,  Hou-Yu Chen

IPC: H01L29/772 ,  H01L21/283 ,  B82Y40/00 ,  B82Y99/00

CPC classification number: B82Y40/00 ,  B82Y10/00 ,  H01L29/0676

Abstract: The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion.

Abstract translation: 本发明公开了一种纳米线制造方法和使用由其制造的纳米线的半导体元件。 本发明的方法包括以下步骤：提供基底; 在基板上依次沉积二氧化硅层和氮化硅层; 在所述氮化硅层上形成图案化的光致抗蚀剂层; 使用图案化的光致抗蚀剂层作为掩模来蚀刻氮化硅层和二氧化硅层，其中衬底被部分蚀刻掉以形成突起; 去除图案化的光致抗蚀剂层以形成隔离层; 去除氮化硅和二氧化硅层，依次沉积介电层和多晶硅层; 并且各向异性地蚀刻多晶硅层以在介电层的位于突起的侧壁周围的区域上形成纳米线。

公开(公告)号：US08048747B1

公开(公告)日：2011-11-01

申请号：US12917690

申请日：2010-11-02

Applicant: Min-Cheng Chen ,  Hou-Yu Chen ,  Chia-Yi Lin

Inventor： Min-Cheng Chen ,  Hou-Yu Chen ,  Chia-Yi Lin

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8236

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833

Abstract: The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device can be easily fabricated with only two extra masks for saving cost. The present disclosure uses a general method for mass-producing TFT and is thus fit for fabricating NAND-type or NOR-type flash memory to be used as embedded memory in a system-on-chip.

Abstract translation: 本公开内容制造了一种嵌入式金属氧化物 - 氮化物 - 氧化物 - 硅（MONOS）存储器件。 存储器件与具有低纵横比的存储器层叠。 存储器件可以容易地制造，只需要两个额外的掩模，以节省成本。 本公开使用用于批量生产TFT的一般方法，因此适合于制造NAND型或NOR型闪存，以用作片上系统中的嵌入式存储器。