公开(公告)号：US20080134120A1

公开(公告)日：2008-06-05

申请号：US11941739

申请日：2007-11-16

申请人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

发明人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The block global placement part configured to roughly place the plurality of blocks in a placement region on a semiconductor substrate. The cell placement setting part configured to set placement positions of the macrocells in the block based on a positioning relationship with the other block and the number of the wiring connections with the other block with respect to each of the plurality of blocks roughly placed by the block global placement part.

摘要翻译： 半导体布局设计装置具有块间连接信息提取部分，块全局放置部分和单元布置设置部分。 块间​​连接信息提取部，被配置为基于网表，库信息，平面图信息和技术信息来提取包括标准单元的多个块和宏小区之间的布线连接数。 块全局放置部分被配置为将多个块粗略放置在半导体衬底上的放置区域中。 所述单元布置设置部分被配置为基于与所述另一块的定位关系以及与所述另一块相对于由所述块大致放置的所述多个块中的每一个的所述布线连接的数量来设置所述块中的所述宏单元的布局位置 全球放置部分。

公开(公告)号：US07831947B2

公开(公告)日：2010-11-09

申请号：US11941739

申请日：2007-11-16

申请人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

发明人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The block global placement part configured to roughly place the plurality of blocks in a placement region on a semiconductor substrate. The cell placement setting part configured to set placement positions of the macrocells in the block based on a positioning relationship with the other block and the number of the wiring connections with the other block with respect to each of the plurality of blocks roughly placed by the block global placement part.

摘要翻译： 半导体布局设计装置具有块间连接信息提取部分，块全局放置部分和单元布置设置部分。 块间​​连接信息提取部，被配置为基于网表，库信息，平面图信息和技术信息来提取包括标准单元的多个块和宏小区之间的布线连接数。 块全局放置部分被配置为将多个块粗略地放置在半导体衬底上的放置区域中。 所述单元布置设置部分被配置为基于与所述另一块的定位关系以及与所述另一块相对于由所述块大致放置的所述多个块中的每一个的所述布线连接的数量来设置所述块中的所述宏单元的布局位置 全球放置部分。

公开(公告)号：US20080120582A1

公开(公告)日：2008-05-22

申请号：US11941748

申请日：2007-11-16

申请人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

发明人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5081

摘要： A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The cell initial placement part configured to initially place the standard cells and the macrocells in an placement region to generate an initial floor plan. The evaluation value calculating part configured to calculate an evaluation value of the floor plan based on distances between a plurality of blocks including the standard cells and the macrocells initially placed by the cell initial placement part and the extracted number of the wiring connections between a plurality of blocks.

摘要翻译： 半导体布局设计装置具有块间连接信息提取部分，单元初始放置部分和评估值。 块间​​连接信息提取部，被配置为基于网表，库信息，平面图信息和技术信息来提取包括标准单元的多个块和宏小区之间的布线连接数。 单元初始放置部分被配置为最初将标准单元和宏单元放置在放置区域中以生成初始平面图。 所述评价值运算部被配置为基于包括所述标准单元的多个块与由所述单元初始化配置部开始配置的宏单元之间的距离以及所提取的多个 块。

公开(公告)号：US07836421B2

公开(公告)日：2010-11-16

申请号：US11941748

申请日：2007-11-16

申请人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

发明人： Shen Wang ,  Tetsuaki Utsumi ,  Mizue Sekine

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5081

摘要： A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The cell initial placement part configured to initially place the standard cells and the macrocells in an placement region to generate an initial floor plan. The evaluation value calculating part configured to calculate an evaluation value of the floor plan based on distances between a plurality of blocks including the standard cells and the macrocells initially placed by the cell initial placement part and the extracted number of the wiring connections between a plurality of blocks.

摘要翻译： 半导体布局设计装置具有块间连接信息提取部分，单元初始放置部分和评估值。 块间​​连接信息提取部，被配置为基于网表，库信息，平面图信息和技术信息来提取包括标准单元的多个块和宏小区之间的布线连接数。 单元初始放置部分被配置为最初将标准单元和宏单元放置在放置区域中以生成初始平面图。 所述评价值运算部被配置为基于包括所述标准单元的多个块与由所述单元初始化配置部开始配置的宏单元之间的距离以及所提取的多个 块。