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公开(公告)号：US09619228B2
公开(公告)日：2017-04-11
申请号：US13073992
申请日：2011-03-28
申请人： Takafumi Yuasa , Hiroaki Nakata , Motoki Kimura , Kazushi Akie
发明人： Takafumi Yuasa , Hiroaki Nakata , Motoki Kimura , Kazushi Akie
CPC分类号： G06F9/30101 , G06F9/30058 , G06F9/30192 , G06F9/322
摘要： The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.
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公开(公告)号：US20090304078A1
公开(公告)日：2009-12-10
申请号：US12473950
申请日：2009-05-28
IPC分类号： H04N7/26
摘要： The variable length decoder has a memory device including a plurality of lookup tables, and sequentially decodes codewords of variable-length codes using the memory device. The decoded values corresponding to the codewords and control information pieces are stored in the lookup tables. In decoding one codeword, one lookup table is selected from among the plurality of lookup tables. In the decode, one decoded value corresponding to the one codeword, and a control information piece for selecting a next lookup table depending on the decoded value and used for a next decode are produced from the selected lookup table in response to the one codeword in parallel.
摘要翻译： 可变长度解码器具有包括多个查找表的存储器件，并且使用该存储器件对可变长度代码的码字进行顺序解码。 对应于码字和控制信息的解码值存储在查找表中。 在解码一个码字时，从多个查找表中选择一个查找表。 在解码中，对应于一个码字的一个解码值和用于根据解码值选择下一个查找表并用于下一个解码的控制信息片段从响应于并行的一个码字的所选查询表产生 。
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3.发明授权公开(公告)号：US08442333B2
公开(公告)日：2013-05-14
申请号：US12401613
申请日：2009-03-10
CPC分类号： H04N19/86 , H04N19/103 , H04N19/124 , H04N19/17 , H04N19/176 , H04N19/436 , H04N19/61
摘要： The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves. Errors are not generated in decoding and the decoded image quality does not deteriorate.
摘要翻译： 本发明提供一种图像编码装置，其不需要跨并行处理区域边界的连续宏块之间的量化参数的引用而不形成切片。 图像编码装置通过从并行处理区域的顶部顺序并行处理对编码对象图像的宏块进行编码，并具有每个并行处理区域的编码元素。 当并行处理区域的顶部宏块的所有量化的正交变换系数为零时，编码元件将一个非零系数加到系数的一部分，使系数不为零。 因此，抑制了每个并行处理区域的顶部宏块中的跳过宏块的生成。 由于不需要切片形成，因此应用了并行处理区域边界的预测，并且提高了编码效率。 在解码中不产生错误，解码的图像质量不会恶化。
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公开(公告)号：US20090245664A1
公开(公告)日：2009-10-01
申请号：US12401613
申请日：2009-03-10
IPC分类号： G06K9/36
CPC分类号： H04N19/86 , H04N19/103 , H04N19/124 , H04N19/17 , H04N19/176 , H04N19/436 , H04N19/61
摘要： The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves. Errors are not generated in decoding and the decoded image quality does not deteriorate.
摘要翻译： 本发明提供一种图像编码装置，其不需要跨并行处理区域边界的连续宏块之间的量化参数的引用而不形成切片。 图像编码装置通过从并行处理区域的顶部顺序并行处理对编码对象图像的宏块进行编码，并具有每个并行处理区域的编码元素。 当并行处理区域的顶部宏块的所有量化的正交变换系数为零时，编码元件将一个非零系数加到系数的一部分，使系数不为零。 因此，抑制了每个并行处理区域的顶部宏块中的跳过宏块的生成。 由于不需要切片形成，因此应用了并行处理区域边界的预测，并且提高了编码效率。 在解码中不产生错误，解码的图像质量不会恶化。
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公开(公告)号：US20110238964A1
公开(公告)日：2011-09-29
申请号：US13073992
申请日：2011-03-28
申请人： Takafumi YUASA , Hiroaki Nakata , Motoki Kimura , Kazushi Akie
发明人： Takafumi YUASA , Hiroaki Nakata , Motoki Kimura , Kazushi Akie
IPC分类号： G06F9/38
CPC分类号： G06F9/30101 , G06F9/30058 , G06F9/30192 , G06F9/322
摘要： The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.
摘要翻译： 数据处理器包括可操作以执行包括在指令集中的指令的CPU。 指令集包括用于读取存储器空间上的数据的加载指令。 根据加载指令读取的数据包括具有数据读取分支出现位区域的格式类型的数据。 CPU包括数据读取分支控制寄存器; 数据读取分支地址寄存器; 和读数据分析单元。 在数据读取分支发生位区域上设置了表示数据读取分支出现的位值的条件下，在数据读取分支发生位区域上设定了表示数据读取分支发生位保持有效的值， 读分支控制寄存器，通过分支到存储在数据读分支地址寄存器中的地址来执行处理之间的切换。
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6.发明申请STREAM PROCESSING APPARATUS, METHOD FOR STREAM PROCESSING AND DATA PROCESSING SYSTEM 审中-公开流程处理设备，流程处理和数据处理系统的方法公开(公告)号：US20090144527A1
公开(公告)日：2009-06-04
申请号：US12324951
申请日：2008-11-28
IPC分类号： G06F9/44
CPC分类号： H04L49/901 , H04L49/90
摘要： The present invention provides a stream processing apparatus capable of improving the processing performance in the case of continuously processing a plurality of data streams. A control stream, different from a data stream, is prepared, and a program and a parameter are updated in advance in accordance with the control stream. Double buffer areas are prepared in a memory of the stream processing apparatus into which the program and the parameter are stored. The location of the data stream to be input is written in the control stream, and buffers for reading the data stream are multiplexed so as to read in advance the top portion of the data stream to be processed next.
摘要翻译： 本发明提供一种在连续处理多个数据流的情况下能够提高处理性能的流处理装置。 准备与数据流不同的控制流，并且根据控制流预先更新程序和参数。 在存储程序和参数的流处理装置的存储器中准备双缓冲区。 要输入的数据流的位置被写入控制流中，并且用于读取数据流的缓冲器被多路复用，以便预先读取接下来要处理的数据流的顶部。
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