公开(公告)号：US20120230374A1

公开(公告)日：2012-09-13

申请号：US13460677

申请日：2012-04-30

Applicant: Thomas J. Kolze ,  Nabil R. Yousef ,  Jonathan S. Min

Inventor： Thomas J. Kolze ,  Nabil R. Yousef ,  Jonathan S. Min

IPC: H04L27/00 ,  H04B1/38

CPC classification number: H04N21/6168 ,  H04B1/71 ,  H04B1/7102 ,  H04B1/7103 ,  H04B1/71055 ,  H04B1/71072 ,  H04B2201/709709 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0045 ,  H04L1/005 ,  H04L1/0057

Abstract: A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication.

公开(公告)号：US07890845B2

公开(公告)日：2011-02-15

申请号：US11692296

申请日：2007-03-28

Applicant: Tracy Denk ,  Chaoliang T. Chen ,  Philip Treigherman ,  Nabil R. Yousef

Inventor： Tracy Denk ,  Chaoliang T. Chen ,  Philip Treigherman ,  Nabil R. Yousef

IPC: H03M13/00

CPC classification number: H04N21/2383 ,  H04N21/4382 ,  H04N21/64315

Abstract: A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.

Abstract translation: 一种在DVB-H接收机中使用的MPE-FEC存储器芯片和方法，其中所述存储器芯片包括TS解复用器; 一个RS解码器; 系统总线 以及RAM单元，其适于通过时分复用同时与TS解复用器，RS解码器和系统总线接口，其中RAM单元适于（i）每时钟周期访问多个字，以及（ii）高速缓存写入 以及读取访问以减少来自TS解复用器和系统总线的存储器访问，并且其中RAM单元适于以高于接口数据路径的速度被计时以增加RAM单元的有效吞吐量。 RAM单元可以包括多个RAM子单元，其中当第一RAM子单元是时钟门控时，剩余的多个RAM子单元是可访问的。

公开(公告)号：US20080151799A1

公开(公告)日：2008-06-26

申请号：US11615292

申请日：2006-12-22

Applicant: Nabil R. Yousef ,  Jun Ma ,  Chaoliang T. Chen

Inventor： Nabil R. Yousef ,  Jun Ma ,  Chaoliang T. Chen

IPC: G08C17/00

CPC classification number: H04N21/443 ,  H04H20/426 ,  H04N21/4382 ,  H04N21/4436 ,  H04N21/64315

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, wherein the method comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; removing an on-chip timer and internal state registers in the DVB-H receiver; and allowing the DVB-H receiver to power off in between receipt of data bursts. Preferably, the removing process reduces the time to perform the re-synchronization in the DVB-H receiver. Preferably, the data bit re-synchronization sequence comprises performing an automatic gain control (AGC) lock process; performing a model and guard detecting process; performing a frequency offset estimation process; performing a transmit parameter signaling (TPS) detection process; performing a timing and carrier loop lock process; and performing an equalizer delay process.

Abstract translation: 一种用于对手持式数字视频广播（DVB-H）接收机执行重新同步的系统和方法，其中所述方法包括对由DVB-H接收机接收的数据位执行时分复用（TDM）数据脉冲串传输序列 ; 在DVB-H接收机上执行数据比特重新同步序列; 去除DVB-H接收机中的片上定时器和内部状态寄存器; 并允许DVB-H接收机在接收到数据脉冲串之间断电。 优选地，去除过程减少了在DVB-H接收机中执行重新同步的时间。 优选地，数据比特重新同步序列包括执行自动增益控制（AGC）锁定过程; 执行模型和保护检测过程; 执行频偏估计处理; 执行传输参数信令（TPS）检测过程; 执行定时和载波循环锁定过程; 并执行均衡器延迟处理。

公开(公告)号：US07366258B2

公开(公告)日：2008-04-29

申请号：US10962803

申请日：2004-10-12

Applicant: Thomas J. Kolze ,  Nabil R. Yousef ,  Jonathan S. Min

Inventor： Thomas J. Kolze ,  Nabil R. Yousef ,  Jonathan S. Min

IPC: H04L27/06

CPC classification number: H04N21/6168 ,  H04B1/71 ,  H04B1/7102 ,  H04B1/7103 ,  H04B1/71055 ,  H04B1/71072 ,  H04B2201/709709 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0045 ,  H04L1/005 ,  H04L1/0057

Abstract: A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication.

Abstract translation: 用于减轻通信系统中的损害的系统包括延迟块，信号电平块，移动平均窗口块，脉冲噪声检测块和组合器。 延迟块在扩展间隔中接收并延迟多个芯片的每个芯片。 信号电平块在扩展间隔中确定多个芯片的每个芯片的信号电平。 移动平均窗口块确定与芯片对应的芯片窗口的复合信号电平。 脉冲噪声检测块接收信号电平，接收复合信号电平，并产生相应芯片窗口的多个芯片的每个芯片的擦除指示。 基于擦除指示，组合器擦除扩展间隔的多个芯片的芯片。

公开(公告)号：US07313122B2

公开(公告)日：2007-12-25

申请号：US10225963

申请日：2002-08-22

Applicant: Nabil R. Yousef ,  Jonathan S. Min ,  Bruce J. Currivan

Inventor： Nabil R. Yousef ,  Jonathan S. Min ,  Bruce J. Currivan

IPC: H04B7/216

CPC classification number: H04L5/026 ,  H04B1/7103 ,  H04L2027/0065

Abstract: “Multiple approaches are presented herein to perform CFO correction within CDMA systems having multiple users. Any communication receiver may be adapted to perform the CFO correction in this manner CDM. One approach assumes a diagonal CFO matrix to decouple the different codes' soft symbol decisions, and each soft symbol decision is independently corrected to obtain hard decisions. Another approach employs direct CFO matrix inversion and multiplies it by a despread soft symbol decision vector to obtain corrected soft symbol decisions. Another approach first performs a single-user correction on the despread soft symbol decisions so, which are then sliced to obtain initial hard decisions. In the next step of this particular approach the initial hard decisions are multiplied by the CFO coefficients to obtain an estimate for the undesired ICI, which is then subtracted from the despread soft symbol decisions to obtain cleaner soft symbol decisions, which then can undergo slicing.”

Abstract translation: 本文提出了多种方法来执行具有多个用户的CDMA系统内的CFO校正。 任何通信接收机可以适于以这种方式执行CFO校正。 一种方法假设对角线CFO矩阵来解耦不同码的软符号决定，并且每个软符号决定被独立地校正以获得硬判决。 另一种方法采用直接CFO矩阵反演，并将其乘以去扩展的软符号决策矢量以获得校正的软符号决定。 另一种方法首先对解扩的软符号决定进行单用户校正，然后对其进行切片以获得初始硬判决。 在该特定方法的下一步骤中，将初始硬判决乘以CFO系数以获得不期望的ICI的估计，然后从解扩的软符号决定中减去该估计，以获得更清洁的软符号决定，然后可以进行切片 。

公开(公告)号：US07308053B2

公开(公告)日：2007-12-11

申请号：US11592286

申请日：2006-11-02

Applicant: Nabil R. Yousef ,  Jun Ma ,  Jonathan S. Min

Inventor： Nabil R. Yousef ,  Jun Ma ,  Jonathan S. Min

IPC: H04L27/06

CPC classification number: H04B1/707 ,  H04B2201/70701 ,  H04L2027/0055

Abstract: Iterative data-aided carrier CFO estimation for CDMA systems. Any communication receiver may be adapted to perform the iterative data-aided carrier CFO estimation. The iterative data-aided carrier CFO estimation is performed using a high accuracy method. The operation may be described as follows: a received signal is despread and buffered. Using the received preamble sequence, an initial estimate of the CFO is obtained. This estimate is used to correct the whole despread data. The corrected data using the initial CFO estimate is sliced. Each despread data symbol is divided by the corresponding sliced data decision. The obtained sequence is then averaged across different codes to obtain a less noisy sequence, which is then used to estimate the CFO again. The procedure can be repeated (iterated) to obtain a more accurate carrier frequency offset estimate; the number of times in which the procedure is repeated may be programmable or predetermined.

Abstract translation: CDMA系统的迭代数据辅助载波CFO估计。 任何通信接收机可以适于执行迭代数据辅助载波CFO估计。 使用高精度方法进行迭代数据辅助载波CFO估计。 该操作可以描述如下：接收信号被解扩和缓冲。 使用接收到的前导序列，获得CFO的初始估计。 该估计用于校正整个解扩数据。 使用初始CFO估计的校正数据被切片。 每个解扩数据符号被相应的切片数据判定划分。 然后将获得的序列在不同的代码之间进行平均，以获得较少的噪声序列，然后将其用于再次估计CFO。 可以重复（迭代）该过程以获得更准确的载波频率偏移估计; 重复该过程的次数可以是可编程的或预定的。

公开(公告)号：US07215727B2

公开(公告)日：2007-05-08

申请号：US10291054

申请日：2002-11-08

Applicant: Nabil R. Yousef ,  Jonathan S. Min

Inventor： Nabil R. Yousef ,  Jonathan S. Min

IPC: H03D1/04 ,  H04B1/38 ,  H04N7/173

CPC classification number: H04B1/1027

Abstract: A communication device constructed according to the present invention detects impulse noise in a preamble sequence. In detecting impulse noise in the preamble sequence the communication device first receive a preamble sequence that includes a plurality of preamble symbols. The communication device then divides the plurality of preamble symbols by at least one known preamble symbol to produce a plurality of preamble gains and/or a plurality of preamble phases corresponding to the plurality of preamble symbols. Finally, the communication device determines, based upon the plurality of preamble gains and/or the plurality of preamble phases, that at least one preamble symbol has been adversely affected by impulse noise. The communication device may discard at least one preamble symbol that has been adversely affected by impulse noise from the plurality of preamble symbols. The communication device may combine non-discarded preamble symbols of the plurality of preamble symbols of the preamble sequence to produce a composite result.

Abstract translation: 根据本发明构造的通信设备检测前导序列中的脉冲噪声。 在检测前导码序列中的脉冲噪声时，通信设备首先接收包括多个前导码符号的前同步码序列。 然后，通信设备将多个前导码符号除以至少一个已知的前导码符号，以产生与多个前导码符号相对应的多个前同步码增益和/或多个前同步码相位。 最后，通信设备基于多个前同步码增益和/或多个前导码相位来确定至少一个前同步码符号已被脉冲噪声所不利地影响。 通信设备可以丢弃已经被来自多个前同步码符号的脉冲噪声不利影响的至少一个前导码符号。 通信设备可以组合前导码序列的多个前同步码符号中的未丢弃的前导码符号以产生复合结果。

公开(公告)号：US07796600B2

公开(公告)日：2010-09-14

申请号：US11755062

申请日：2007-05-30

Applicant: Chaoliang T. Chen ,  Tracy Denk ,  Nabil R. Yousef ,  Philip Treigherman

Inventor： Chaoliang T. Chen ,  Tracy Denk ,  Nabil R. Yousef ,  Philip Treigherman

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04H40/18 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/6505 ,  H03M13/6541

Abstract: Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2M consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.

Abstract translation: 位置高速缓存存储器架构，其每帧仅需要32Kb或更小的存储擦除信息，其中简单的地址映射到主MPE-FEC RAM，以便于列和逐行访问。 设计了替代架构，大大减少了MPE-FEC擦除缓存存储器的大小和逻辑复杂度。 相应地，两种体系结构将擦除缓存大小降低到32Kbits和28Kbits，而不引入额外的擦除位置，而另一种架构进一步将所需的存储器容量降低到16K，8K，4K或2K位，总共略微增加 擦除位置。 所有架构将MPE-FEC帧存储器中的数据分组为2M个连续字节的块，并使用一个或几个位来存储每个块中的擦除状态，从而大大减少了所需的高速缓存存储器大小。

公开(公告)号：US07729462B2

公开(公告)日：2010-06-01

申请号：US11615274

申请日：2006-12-22

Applicant: Jun Ma ,  Chaoliang T. Chen ,  Nabil R. Yousef

Inventor： Jun Ma ,  Chaoliang T. Chen ,  Nabil R. Yousef

IPC: H04L7/00

CPC classification number: H04L27/2655 ,  H04L27/266 ,  H04L27/2662 ,  H04L27/2685 ,  H04N21/4382 ,  H04N21/64315

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; and reducing a re-acquisition time at every stage of the data bit re-synchronization sequence, wherein the reducing process results in a reduction in the time to perform the re-synchronization for the DVB-H receiver, wherein the reduction in the time to perform the re-synchronization for the DVB-H receiver is greater than one-half of the time required to perform the re-synchronization for the DVB-H receiver absent the reducing of the re-acquisition time at every stage of the data bit re-synchronization sequence.

Abstract translation: 对DVB-H数字视频广播（DVB-H）接收机执行重新同步的系统和方法包括对由DVB-H接收机接收的数据的比特执行时分复用（TDM）数据突发传输序列; 在DVB-H接收机上执行数据比特重新同步序列; 并且在数据比特重新同步序列的每个阶段减少重新采集时间，其中减少处理导致对DVB-H接收机执行重新同步的时间的减少，其中将时间缩短 执行DVB-H接收机的重新同步大于执行DVB-H接收机的重新同步所需的时间的一半，而不需要在数据比特的每个阶段减少重新获取时间 - 同步序列。

公开(公告)号：US20100111141A1

公开(公告)日：2010-05-06

申请号：US12651945

申请日：2010-01-04

Applicant: Bruce J. Currivan ,  Nabil R. Yousef ,  Thomas J. Kolze ,  Gottfried Ungerboeck

Inventor： Bruce J. Currivan ,  Nabil R. Yousef ,  Thomas J. Kolze ,  Gottfried Ungerboeck

IPC: H04B1/707

CPC classification number: H04B7/216 ,  H04B1/71 ,  H04B1/7107 ,  H04J13/0003 ,  H04J13/16 ,  H04L25/03038 ,  H04L25/03343 ,  H04L25/49 ,  H04L27/3405 ,  H04L2025/03375 ,  H04L2025/03477

Abstract: A communication system performs burst noise cancellation. A transmitter produces and transmits a spread signal that comprises at least one known-value symbol spread by a plurality of non data-carrying orthogonal codes and data symbols spread by at least one data-carrying orthogonal code. The transmitter transmits the spread signal across a communication link that introduces burst noise. A burst noise detector determines burst noise affected chips of the orthogonal codes. A weight computation functional block calculates a plurality of complex-valued combining weights based upon the burst noise affected chips. A vector de-spreader and a linear combiner operate in combination to use the plurality of non data-carrying orthogonal codes, the at least one data-carrying orthogonal code, and the plurality of complex-valued combining weights to de-spread the received spread signal to produce the data symbols with the burst noise substantially removed.