-
1.发明申请公开(公告)号：US20080298394A1
公开(公告)日：2008-12-04
申请号：US11755062
申请日：2007-05-30
Applicant: Chaoliang T. Chen , Tracy Denk , Nabil R. Yousef , Philip Treigherman
Inventor： Chaoliang T. Chen , Tracy Denk , Nabil R. Yousef , Philip Treigherman
CPC classification number: H04H40/18 , H03M13/1515 , H03M13/373 , H03M13/6505 , H03M13/6541
Abstract: Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2M consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.
Abstract translation: 位置高速缓存存储器架构，其每帧仅需要32Kb或更小的存储擦除信息，其中简单的地址映射到主MPE-FEC RAM，以便于列和逐行访问。 设计了替代架构，大大减少了MPE-FEC擦除缓存存储器的大小和逻辑复杂度。 相应地，两种体系结构将擦除缓存大小降低到32Kbits和28Kbits，而不引入额外的擦除位置，而另一种架构进一步将所需的存储器容量降低到16K，8K，4K或2K位，总共略微增加 擦除位置。 所有架构将MPE-FEC帧存储器中的数据分组为2M个连续字节的块，并使用一个或几个位来存储每个块中的擦除状态，从而大大减少了所需的高速缓存存储器大小。
-
公开(公告)号：US20050171986A1
公开(公告)日：2005-08-04
申请号：US11091639
申请日：2005-03-28
Applicant: Tracy Denk , Jeffrey Putnam
Inventor： Tracy Denk , Jeffrey Putnam
CPC classification number: G06F7/49942 , G06F7/48 , G06F7/49963
Abstract: Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectable bias, a reduced precision signal, having minimized or eliminated rounding error, is generated. The selectable bias corresponds to a predetermined characteristic of one of bias, an error signal, the input datum, the reduced precision datum, and a combination thereof.
-
公开(公告)号：US08659706B2
公开(公告)日：2014-02-25
申请号：US13899311
申请日：2013-05-21
Applicant: James Carwana , Jun Tang , Philip Treigherman , Chaoliang T. Chen , Tracy Denk
Inventor： James Carwana , Jun Tang , Philip Treigherman , Chaoliang T. Chen , Tracy Denk
CPC classification number: H04N5/45 , H04N5/455 , H04N21/4263 , H04N21/4305 , H04N21/4316 , H04N21/6112
Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.
Abstract translation: 多芯片天线分集架构和方法包括从第一天线接收第一输入信号的第一接收器芯片。 第一接收器芯片包括放大第一输入信号的第一调谐器，可操作地连接到第一晶体振荡器电路的晶体和从第一晶体振荡器电路接收时钟信号的第一晶体振荡器时钟缓冲器。 第一解调器解调从第一调谐器接收的输入信号。 第二接收器芯片从第二天线接收第二输入信号。 第二接收器芯片包括从第一解调器接收分集数据的第二晶体振荡器电路，第二晶体振荡器时钟缓冲器，第二调谐器和第二解调器。 第一晶体振荡器时钟缓冲器将时钟信号驱动到第二晶体振荡器时钟缓冲器，第二调谐器和第二接收器芯片的第二解调器。
-
公开(公告)号：US20130251072A1
公开(公告)日：2013-09-26
申请号：US13899388
申请日：2013-05-21
Applicant: James Carwana , Chaoliang T. Chen , Tracy Denk
Inventor： James Carwana , Chaoliang T. Chen , Tracy Denk
IPC: H04B7/08
CPC classification number: H04B7/08 , H04B7/0857 , H04W52/0229 , Y02D70/444
Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.
Abstract translation: 多芯片天线分集架构包括第一接收器芯片，包括第一调谐器和直接连接到调谐器的第一解调器。 第一解调器解调从第一调谐器接收的第一输入信号。 控制第一接收器芯片的第一电源定序器和包括指示第一接收器芯片作为从芯片的电压源VSS的第一芯片ID。 第二接收器芯片包括第二调谐器和直接连接到第二调谐器的第二解调器。 第二解调器解调从第二调谐器接收的第二输入信号。 直接连接到第二解调器的第二分集组合器。 第二芯片ID包括指示第二接收器芯片作为主芯片的电压源VDD。 分集状态机（DSM）控制结构相同的第一接收机芯片和第二接收机芯片的操作状态。
-
公开(公告)号：US20120063553A1
公开(公告)日：2012-03-15
申请号：US12882174
申请日：2010-09-14
Applicant: James Carwana , Chaoliang T. Chen , Tracy Denk
Inventor： James Carwana , Chaoliang T. Chen , Tracy Denk
CPC classification number: H04B7/08 , H04B7/0857 , H04W52/0229 , Y02D70/444
Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.
Abstract translation: 多芯片天线分集架构包括第一接收器芯片，包括第一调谐器和直接连接到调谐器的第一解调器。 第一解调器解调从第一调谐器接收的第一输入信号。 控制第一接收器芯片的第一电源定序器和包括指示第一接收器芯片作为从芯片的电压源VSS的第一芯片ID。 第二接收器芯片包括第二调谐器和直接连接到第二调谐器的第二解调器。 第二解调器解调从第二调谐器接收的第二输入信号。 直接连接到第二解调器的第二分集组合器。 第二芯片ID包括指示第二接收器芯片作为主芯片的电压源VDD。 分集状态机（DSM）控制结构相同的第一接收机芯片和第二接收机芯片的操作状态。
-
Patent Agency Ranking
公开(公告)号：US07890845B2
公开(公告)日：2011-02-15
申请号：US11692296
申请日：2007-03-28
Applicant: Tracy Denk , Chaoliang T. Chen , Philip Treigherman , Nabil R. Yousef
Inventor： Tracy Denk , Chaoliang T. Chen , Philip Treigherman , Nabil R. Yousef
IPC: H03M13/00
CPC classification number: H04N21/2383 , H04N21/4382 , H04N21/64315
Abstract: A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.
Abstract translation: 一种在DVB-H接收机中使用的MPE-FEC存储器芯片和方法，其中所述存储器芯片包括TS解复用器; 一个RS解码器; 系统总线 以及RAM单元，其适于通过时分复用同时与TS解复用器，RS解码器和系统总线接口，其中RAM单元适于（i）每时钟周期访问多个字，以及（ii）高速缓存写入 以及读取访问以减少来自TS解复用器和系统总线的存储器访问，并且其中RAM单元适于以高于接口数据路径的速度被计时以增加RAM单元的有效吞吐量。 RAM单元可以包括多个RAM子单元，其中当第一RAM子单元是时钟门控时，剩余的多个RAM子单元是可访问的。
-
公开(公告)号：US08681908B2
公开(公告)日：2014-03-25
申请号：US13899388
申请日：2013-05-21
Applicant: James Carwana , Chaoliang T. Chen , Tracy Denk
Inventor： James Carwana , Chaoliang T. Chen , Tracy Denk
CPC classification number: H04B7/08 , H04B7/0857 , H04W52/0229 , Y02D70/444
Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.
Abstract translation: 多芯片天线分集架构包括第一接收器芯片，包括第一调谐器和直接连接到调谐器的第一解调器。 第一解调器解调从第一调谐器接收的第一输入信号。 控制第一接收器芯片的第一电源定序器和包括指示第一接收器芯片作为从芯片的电压源VSS的第一芯片ID。 第二接收器芯片包括第二调谐器和直接连接到第二调谐器的第二解调器。 第二解调器解调从第二调谐器接收的第二输入信号。 直接连接到第二解调器的第二分集组合器。 第二芯片ID包括指示第二接收器芯片作为主芯片的电压源VDD。 分集状态机（DSM）控制结构相同的第一接收机芯片和第二接收机芯片的操作状态。
-
8.发明授权公开(公告)号：US07796600B2
公开(公告)日：2010-09-14
申请号：US11755062
申请日：2007-05-30
Applicant: Chaoliang T. Chen , Tracy Denk , Nabil R. Yousef , Philip Treigherman
Inventor： Chaoliang T. Chen , Tracy Denk , Nabil R. Yousef , Philip Treigherman
CPC classification number: H04H40/18 , H03M13/1515 , H03M13/373 , H03M13/6505 , H03M13/6541
Abstract: Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2M consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.
Abstract translation: 位置高速缓存存储器架构，其每帧仅需要32Kb或更小的存储擦除信息，其中简单的地址映射到主MPE-FEC RAM，以便于列和逐行访问。 设计了替代架构，大大减少了MPE-FEC擦除缓存存储器的大小和逻辑复杂度。 相应地，两种体系结构将擦除缓存大小降低到32Kbits和28Kbits，而不引入额外的擦除位置，而另一种架构进一步将所需的存储器容量降低到16K，8K，4K或2K位，总共略微增加 擦除位置。 所有架构将MPE-FEC帧存储器中的数据分组为2M个连续字节的块，并使用一个或几个位来存储每个块中的擦除状态，从而大大减少了所需的高速缓存存储器大小。
-
公开(公告)号：US08594256B2
公开(公告)日：2013-11-26
申请号：US12882174
申请日：2010-09-14
Applicant: James Carwana , Chaoliang T. Chen , Tracy Denk
Inventor： James Carwana , Chaoliang T. Chen , Tracy Denk
CPC classification number: H04B7/08 , H04B7/0857 , H04W52/0229 , Y02D70/444
Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.
Abstract translation: 多芯片天线分集架构包括第一接收器芯片，包括第一调谐器和直接连接到调谐器的第一解调器。 第一解调器解调从第一调谐器接收的第一输入信号。 控制第一接收器芯片的第一电源定序器和包括指示第一接收器芯片作为从芯片的电压源VSS的第一芯片ID。 第二接收器芯片包括第二调谐器和直接连接到第二调谐器的第二解调器。 第二解调器解调从第二调谐器接收的第二输入信号。 直接连接到第二解调器的第二分集组合器。 第二芯片ID包括指示第二接收器芯片作为主芯片的电压源VDD。 分集状态机（DSM）控制结构相同的第一接收机芯片和第二接收机芯片的操作状态。
-
公开(公告)号：US20130271662A1
公开(公告)日：2013-10-17
申请号：US13899311
申请日：2013-05-21
Applicant: James Carwana , Jun Tang , Philip Treigherman , Chaoliang T. Chen , Tracy Denk
Inventor： James Carwana , Jun Tang , Philip Treigherman , Chaoliang T. Chen , Tracy Denk
IPC: H04N5/45
CPC classification number: H04N5/45 , H04N5/455 , H04N21/4263 , H04N21/4305 , H04N21/4316 , H04N21/6112
Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.
Abstract translation: 多芯片天线分集架构和方法包括从第一天线接收第一输入信号的第一接收器芯片。 第一接收器芯片包括放大第一输入信号的第一调谐器，可操作地连接到第一晶体振荡器电路的晶体和从第一晶体振荡器电路接收时钟信号的第一晶体振荡器时钟缓冲器。 第一解调器解调从第一调谐器接收的输入信号。 第二接收器芯片从第二天线接收第二输入信号。 第二接收器芯片包括从第一解调器接收分集数据的第二晶体振荡器电路，第二晶体振荡器时钟缓冲器，第二调谐器和第二解调器。 第一晶体振荡器时钟缓冲器将时钟信号驱动到第二晶体振荡器时钟缓冲器，第二调谐器和第二接收器芯片的第二解调器。
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.01 seconds)
