公开(公告)号：US07093190B1

公开(公告)日：2006-08-15

申请号：US10194816

申请日：2002-07-12

申请人： John S. Kuslak ,  Nadeem T. Chaudhry ,  Ashiqur Rahman

发明人： John S. Kuslak ,  Nadeem T. Chaudhry ,  Ashiqur Rahman

IPC分类号： G11C29/00

CPC分类号： G11C7/24 ,  G06F11/1032 ,  G06F12/126

摘要： A method and apparatus is provided for handling parity errors within a data processing system. Each occurrence of a parity error is attributed to an addressable memory location or a block of memory locations that was being accessed when the error occurred. A memory location or a memory block is marked as unusable after a predetermined number of errors is attributed to that location or block, respectively. The predetermined number of errors that is allowed to occur prior to degradation could be two, or more. In one embodiment, the predetermined number of errors resulting in memory degradation is programmable.

摘要翻译： 提供了一种用于处理数据处理系统内的奇偶校验错误的方法和装置。 每次出现奇偶校验错误都归因于可寻址的存储器位置或发生错误时正在访问的存储器单元块。 在预定数量的错误分别归因于该位置或块之后，存储器位置或存储器块被标记为不可用。 在劣化之前允许发生的预定数量的错误可以是两个或更多个。 在一个实施例中，导致存储器劣化的预定数量的错误是可编程的。