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    MEMORY SYSTEM WITH ERROR DETECTION
    1.
    发明公开
    MEMORY SYSTEM WITH ERROR DETECTION 审中-公开

    公开(公告)号：US20230307079A1

    公开(公告)日：2023-09-28

    申请号：US18295445

    申请日：2023-04-04

    申请人： Rambus Inc.

    发明人： Frederick A. Ware ,  John Eric Linstadt

    IPC分类号： G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G06F11/10

    CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401 ,  G06F11/1012 ,  G06F11/1016 ,  G06F11/1032 ,  G06F11/1048

    摘要： A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

    ERROR VECTOR READOUT FROM A MEMORY DEVICE
    6.
    发明申请
    ERROR VECTOR READOUT FROM A MEMORY DEVICE 有权
    错误的向量从存储器设备中读取

    公开(公告)号：US20160328285A1

    公开(公告)日：2016-11-10

    申请号：US14724901

    申请日：2015-05-29

    申请人： International Business Machines Corporation

    发明人： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

    IPC分类号： G06F11/10 ,  G06F3/06

    CPC分类号： G06F11/1008 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/08 ,  G06F11/1032 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1051 ,  G11C29/52 ,  G11C2029/0411

    摘要： A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

    摘要翻译： 描述了存储管理系统和管理由存储原始数据和纠错编码（ECC）位的存储器件产生的输出数据的方法。 该系统包括控制器，用于接收读取命令并基于读取命令控制存储器件，存储器件存储原始数据和纠错编码（ECC）位，并输出与指定的存储器地址对应的原始数据和ECC位 在读取命令中，以及ECC解码器，基于原始数据和与存储器件输出的存储器地址相对应的ECC位来输出与存储器地址相关联的错误向量，与存储器地址相关联的错误向量指示错误 原始数据对应于存储器地址。 该系统还包括多路复用器（MUX），用于根据读取命令中指示的选择来输出误差向量。

    Method for handling interrupted writes using multiple cores
    7.
    发明授权
    Method for handling interrupted writes using multiple cores 有权
    使用多个内核处理中断写入的方法

    公开(公告)号：US09400716B2

    公开(公告)日：2016-07-26

    申请号：US14805667

    申请日：2015-07-22

    申请人： NetApp, Inc.

    发明人： Mahmoud K. Jibbe ,  Senthil Kannan ,  Selvaraj Rasappan

    IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11B20/18

    CPC分类号： G06F11/1076 ,  G06F11/1032 ,  G06F11/2092 ,  G11B20/1833 ,  G11B2220/415

    摘要： An apparatus including a storage array, a primary controller, a secondary controller and a solid state device. The storage array may be configured to be accessed by a plurality of controllers. A first of the plurality of the controllers may be configured as the primary controller configured to read and write to and from the storage array during a normal condition. A second of the plurality of the controllers may be configured as the secondary controller configured to read and write to and from the storage array during a fault condition. The solid state device may be configured to (i) store data and (ii) be accessed by the storage array and the secondary controller.

    摘要翻译： 一种包括存储阵列，主控制器，辅助控制器和固态设备的装置。 存储阵列可以被配置为被多个控制器访问。 多个控制器中的第一个可以被配置为主要控制器，其被配置为在正常状态期间从存储阵列读取和写入存储阵列。 多个控制器中的第二个可以被配置为辅助控制器，其被配置为在故障状态期间从存储阵列读取和写入存储阵列。 固态设备可以被配置为（i）存储数据和（ii）由存储阵列和辅助控制器访问。

    Nonvolatile logic array and power domain segmentation in processing device
    8.
    发明授权
    Nonvolatile logic array and power domain segmentation in processing device 有权
    非易失性逻辑阵列和功率域分割处理器件

    公开(公告)号：US09342259B2

    公开(公告)日：2016-05-17

    申请号：US13770498

    申请日：2013-02-19

    申请人： Texas Instruments Incorporated

    发明人： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC分类号： G06F1/00 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10

    CPC分类号： G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    摘要： A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.

    摘要翻译： 计算设备包括与第一功能相关联的第一组非易失性逻辑元件阵列和与第二功能相关联的第二组非易失性逻辑元件阵列。 第一组和第二组非易失性逻辑元件阵列是独立可控的。 第一电源域向计算设备的交换逻辑元件供电，第二电源域为配置成控制用于将数据存储到非易失性逻辑单元阵列或从非易失性逻辑单元阵列读取数据的信号的逻辑元件供电，而第三电源域供电 用于非易失性逻辑元件阵列。 基于系统状态，不同的电源域被独立上电或下电，以减少在冗余逻辑切换期间的功率损耗以及在恢复系统状态期间伴随的寄生功率消耗，并且在计算的常规操作期间减少备用存储元件的功率泄漏 设备。

    Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
    10.
    发明授权
    Nonvolatile logic array with retention flip flops to reduce switching power during wakeup 有权
    具有保持触发器的非易失性逻辑阵列，以降低唤醒期间的开关电源

    公开(公告)号：US09058126B2

    公开(公告)日：2015-06-16

    申请号：US13770368

    申请日：2013-02-19

    申请人： Texas Instruments Incorporated

    发明人： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC分类号： G06F12/10 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14

    CPC分类号： G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    摘要： A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.

    摘要翻译： 使用多个易失性存储元件来操作处理装置。 多个易失性存储元件中的数据被存储在多个非易失性逻辑元件阵列中。 多个易失性存储元件中的各个易失性存储元件的主要逻辑电路部分由第一电源域供电，并且多个易失性存储元件中的单个的易失性存储元件的从属级电路部分由第二电源域供电。 在从多个非易失性逻辑单元阵列向多个易失性存储元件的数据写回期间，第一功率域被断电并维持第二功率域。 在另一种方法中，多个非易失性逻辑单元阵列由第三功率域供电，该第三功率域在处理设备的常规操作期间被关断。