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公开(公告)号：US20090276683A1
公开(公告)日：2009-11-05
申请号：US12515176
申请日：2006-11-17
CPC分类号： H03M13/19
摘要： A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.
摘要翻译： 发射机与接收机通信，误差校正器校正数据传输期间产生的比特错误。 发射机具有扰频单元，用于加扰数据，使得输入数据中的0和1的运行视差基本上为零。 一个比特串转换单元15，其添加用于确保加扰数据的串行比特串的最大游程长度的比特数据，并将控制信息转换成固定值的比特数据。 同步定时生成单元16将发送的数据以恒定的间隔分割，并将发送数据转换为数据块。 位串转换单元从数据块的位串中提取控制数据的固定值位模式，将位模式转换为控制信息，并对数据和控制信息进行鉴别。 解扰器单元将数据加扰的数据重新转换为加扰之前的数据。
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2.发明申请公开(公告)号：US20120213075A1
公开(公告)日：2012-08-23
申请号：US13397292
申请日：2012-02-15
申请人： Naohisa Koie , Teruo Kaganoi , Takeshi Aimoto
发明人： Naohisa Koie , Teruo Kaganoi , Takeshi Aimoto
IPC分类号： H04L12/26
CPC分类号： H04L47/2441
摘要： It is intended to reduce a power consumption without degrading a communication quality of a packet transfer device. One or more of a receiver, a switch unit, and a transmitter include a QoS control circuit for applying QoS control to received packets. There is provided a power saving operation mode that enables power saving operation by changing a grain size of the QoS control according to a flow rate of the packets, and controlling whether or not to supply an electric power to the QoS control circuit or a part of the QoS control circuit, according to the flow rate of the packets.
摘要翻译： 旨在降低功耗而不降低分组传送装置的通信质量。 接收机，交换机单元和发射机中的一个或多个包括用于对接收的分组应用QoS控制的QoS控制电路。 提供了一种省电操作模式，其通过根据分组的流量改变QoS控制的粒度来进行节能操作，并且控制是否向QoS控制电路或部分服务提供电力 QoS控制电路，根据报文的流量。
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公开(公告)号：US20080026693A1
公开(公告)日：2008-01-31
申请号：US10589978
申请日：2004-09-09
CPC分类号： H04B7/15521
摘要： The objective of the present invention is to improve transmission characteristics by transmitting data through multiple paths in a multihop radio network including multiple paths.In a source node 210 of (a), an encoder 212 performs communication path encoding, and a modulator 216 modulates. Unlike the prior art, however, a packetizing unit 214 designates relay paths and packetizes outputs from the encoder 212 for the respective paths, whereby signals are transmitted to multiple paths (in this case, two paths). A receiver (See (c)) of a destination node 260 demodulates the signals from the multiple paths using a demodulator 262. Thereafter, it depacketizes the packet of binary data hard-decided by a depacketizing/buffering unit 263 and then temporarily stores the depacketized pieces of data for respective paths in a buffer. A reliability data calculator 265 then diversity-combines, taking reliability data into account. A combiner/decoder 267 performs an error correction based on that combined data.
摘要翻译： 本发明的目的是通过在包括多个路径的多跳无线电网络中通过多条路径发送数据来改善传输特性。 在（a）的源节点210中，编码器212执行通信路径编码，调制器216进行调制。 然而，与现有技术不同，打包单元214指定中继路径并对来自编码器212的各路径的输出进行分组，由此将信号发送到多条路径（在这种情况下为两条路径）。 目的地节点260的接收机（见（c））使用解调器262解调来自多个路径的信号。 此后，由解包/缓冲单元263硬判断二进制数据包，然后临时存储缓冲器中的相应路径的解封装数据段。 然后，可靠性数据计算器265对可靠性数据进行分集组合。 组合器/解码器267基于该组合数据进行纠错。
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公开(公告)号：US08281207B2
公开(公告)日：2012-10-02
申请号：US12515176
申请日：2006-11-17
IPC分类号： H03M13/00
CPC分类号： H03M13/19
摘要： A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.
摘要翻译： 发射机与接收机通信，误差校正器校正数据传输期间产生的比特错误。 发射机具有扰频单元，用于加扰数据，使得输入数据中的0和1的运行视差基本上为零。 一个比特串转换单元15，其添加用于确保加扰数据的串行比特串的最大游程长度的比特数据，并将控制信息转换成固定值的比特数据。 同步定时生成单元16将发送的数据以恒定的间隔分割，并将发送数据转换为数据块。 位串转换单元从数据块的位串中提取控制数据的固定值位模式，将位模式转换为控制信息，并对数据和控制信息进行鉴别。 解扰器单元将数据加扰的数据重新转换为加扰之前的数据。
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公开(公告)号：US09712449B2
公开(公告)日：2017-07-18
申请号：US13397292
申请日：2012-02-15
申请人： Naohisa Koie , Teruo Kaganoi , Takeshi Aimoto
发明人： Naohisa Koie , Teruo Kaganoi , Takeshi Aimoto
IPC分类号： H04L12/26 , H04L12/54 , H04L12/801 , H04L12/851
CPC分类号： H04L47/2441
摘要： It is intended to reduce a power consumption without degrading a communication quality of a packet transfer device. One or more of a receiver, a switch unit, and a transmitter include a QoS control circuit for applying QoS control to received packets. There is provided a power saving operation mode that enables power saving operation by changing a grain size of the QoS control according to a flow rate of the packets, and controlling whether or not to supply an electric power to the QoS control circuit or a part of the QoS control circuit, according to the flow rate of the packets.
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