公开(公告)号：US07685496B2

公开(公告)日：2010-03-23

申请号：US10579047

申请日：2004-07-22

申请人： Hidehiro Toyoda

发明人： Hidehiro Toyoda

IPC分类号： H03M13/00

CPC分类号： H04L1/0057 ,  H04J14/02 ,  H04J14/0226 ,  H04J14/0279 ,  H04L1/0041 ,  H04L2001/0096

摘要： In a method for data transmission, which transmits data through a transmission line, which integrates a plurality of links into one transmission line, a first link group, which transmits information data by at least one link out of a plurality of links, a second link group, which transmits parity data generated by the information data by at least one link out of a plurality of links, which are different from the first link group, and a third link group, which generates an error check data related to an error correction from the information data or the parity data, when an error occurs in the information data or the parity data, and transmits by at least one link out of a plurality of links, which are different from the first link group and the second link group, are integrated and transmitted.

摘要翻译： 在通过将多个链路集成到一个传输线中的传输线传输数据的数据传输方法中，通过多个链路中的至少一个链路发送信息数据的第一链路组，第二链路 组，其通过由与第一链路组不同的多个链路中的至少一个链路发送由信息数据生成的奇偶校验数据;以及第三链路组，其生成与错误校正有关的错误校验数据， 信息数据或奇偶校验数据，当在信息数据或奇偶校验数据中出现错误时，通过与第一链路组和第二链路组不同的多个链路中的至少一个链路进行发送时， 集成和传输。

公开(公告)号：US20080056342A1

公开(公告)日：2008-03-06

申请号：US11782705

申请日：2007-07-25

申请人： KOJI FUJUDA ,  Hidehiro Toyoda ,  Hiroki Yamashita

发明人： KOJI FUJUDA ,  Hidehiro Toyoda ,  Hiroki Yamashita

IPC分类号： H03H21/00

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10194 ,  G11B20/10481 ,  G11B2220/2537

摘要： In pulse width control equalization, attention is paid to the existence of the symmetry of anteroposterior signals and thereby the size of a table in which the adjustment amount of an edge position is stored is reduced to the power of one-half. Pattern jitters caused by inter-symbol interference are suppressed. The pulse time span of each symbol is adjusted to an optimum pulse width determined by a calculating formula or search in a table in response to a code sequence to be transmitted. In the configuration wherein a table is used, the table to store an edge position adjustment amount wherein the row of the exclusive OR of two symbols located at positions symmetrical to each other before and after a center symbol now ready to be sent in the code sequence is used as a search key is made.

摘要翻译： 在脉冲宽度控制均衡中，注意前后信号的对称性的存在，从而将存储边缘位置的调整量的表的尺寸减小到二分之一的幂。 由符号间干扰引起的模式抖动被抑制。 每个符号的脉冲时间间隔被调整为由计算公式确定的最佳脉冲宽度或响应于要发送的代码序列在表中搜索。 在使用表格的结构中，存储边缘位置调整量的表，其中位于现在准备好以代码序列发送的中心符号之前和之后彼此对称的两个符号的异或的行 被用作搜索键。

公开(公告)号：US08855148B2

公开(公告)日：2014-10-07

申请号：US13586076

申请日：2012-08-15

申请人： Hidehiro Toyoda ,  Masashi Kono

发明人： Hidehiro Toyoda ,  Masashi Kono

IPC分类号： H04J3/02 ,  H04L29/04 ,  H04L12/26 ,  H04B1/00 ,  H03K17/00 ,  H04J3/00

CPC分类号： H04L12/26 ,  H03K17/00 ,  H03L7/081 ,  H03L7/1976 ,  H04B1/00 ,  H04J3/00 ,  H04J3/047 ,  H04J3/062 ,  H04J3/0685 ,  H04L29/04 ,  H04L43/00

摘要： Digital signals having respective pieces of frequency information different from each other are bundled, and transmitted at high speed. On receiving side, digital signals retaining the respective pieces of frequency information are recovered and separated. Transmitter apparatus divides pieces of transmission data that have the different pieces of frequency information and correspond to respective input channels into data blocks having a fixed length, as valid data, and subsequently multiplexes the data blocks corresponding to the respective input channels and outputs the multiplexed data to a transmission path. A receiver apparatus divides data string received into data flows and subsequently restores the transmission data, from the data blocks consecutive in each data flow and stores the restored data, and outputs transmission data corresponding to the respective data flows in synchronization with clocks generated for these data flows.

摘要翻译： 具有彼此不同的各个频率信息的数字信号被捆扎，并以高速发送。 在接收侧，保存各个频率信息的数字信号被恢复和分离。 发射机设备将具有不同频率信息的传输数据片段与对应于输入信道的传输数据分成具有固定长度的数据块作为有效数据，然后将与各个输入信道相对应的数据块多路复用，并输出多路复用数据 到传输路径。 接收机设备将接收到的数据串分成数据流，然后从每个数据流中连续的数据块中恢复发送数据，并存储恢复的数据，并且与为这些数据生成的时钟同步地输出与各个数据流对应的发送数据 流动。

公开(公告)号：US08498204B2

公开(公告)日：2013-07-30

申请号：US12716451

申请日：2010-03-03

申请人： Hidehiro Toyoda ,  Shinji Murai

发明人： Hidehiro Toyoda ,  Shinji Murai

IPC分类号： H04L12/26

CPC分类号： H04L43/065 ,  H04L1/20 ,  H04L41/0677

摘要： It is provided a data transmission system comprising a transmitter, a repeater and a receiver. The transmitter and the repeater are coupled through a first transmission path and the receiver and the repeater are coupled through a second transmission path. The transmitter, the repeater and the receiver have virtual lanes. The transmitter demultiplexes the transmission data into as many data streams as a number of useable virtual lanes based on useable lane information. The repeater monitors failures of the transmission lanes of the first transmission path and the virtual lanes. The receiver monitors failures of the transmission lanes of the second transmission path and the virtual lanes, selects the useable virtual lanes, sends to the transmitter the useable lane information, corrects a wrong order of the received data streams and a shift of reception point in the virtual lanes, and restores the demultiplexed data streams into the transmission data.

摘要翻译： 提供了一种包括发射机，中继器和接收机的数据传输系统。 发射机和中继器通过第一传输路径耦合，并且接收机和中继器通过第二传输路径耦合。 发射机，中继器和接收机都有虚拟通道。 发射机基于可用的车道信息将传输数据解复用成与许多可用的虚拟车道一样多的数据流。 中继器监视第一传输路径和虚拟通道的传输通道的故障。 接收机监视第二传输路径和虚拟通道的传输通道的故障，选择可用的虚拟通道，向发射机发送可用的车道信息，校正接收到的数据流的错误顺序和接收点的移位 虚拟通道，并将解复用的数据流恢复为传输数据。

公开(公告)号：US08281207B2

公开(公告)日：2012-10-02

申请号：US12515176

申请日：2006-11-17

申请人： Hidehiro Toyoda ,  Takayuki Muranaka ,  Takeshi Matsumoto ,  Naohisa Koie

发明人： Hidehiro Toyoda ,  Takayuki Muranaka ,  Takeshi Matsumoto ,  Naohisa Koie

IPC分类号： H03M13/00

CPC分类号： H03M13/19

摘要： A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.

摘要翻译： 发射机与接收机通信，误差校正器校正数据传输期间产生的比特错误。 发射机具有扰频单元，用于加扰数据，使得输入数据中的0和1的运行视差基本上为零。 一个比特串转换单元15，其添加用于确保加扰数据的串行比特串的最大游程长度的比特数据，并将控制信息转换成固定值的比特数据。 同步定时生成单元16将发送的数据以恒定的间隔分割，并将发送数据转换为数据块。 位串转换单元从数据块的位串中提取控制数据的固定值位模式，将位模式转换为控制信息，并对数据和控制信息进行鉴别。 解扰器单元将数据加扰的数据重新转换为加扰之前的数据。

公开(公告)号：US20060269025A1

公开(公告)日：2006-11-30

申请号：US11350085

申请日：2006-02-09

申请人： Hidehiro Toyoda

发明人： Hidehiro Toyoda

IPC分类号： H04B1/10 ,  G06F17/10

CPC分类号： H03H17/06 ,  H03H17/0294 ,  H03H2220/08 ,  H04B3/10

摘要： Provided is a transversal filter, in which delayers and multipliers are connected in series, includes: a first multiplier for multiplying a first tap coefficient set by a tap coefficient register module and an input signal to output a result of multiplication; a first delayer for delaying the value output from the first multiplier by a predetermined time to output the delayed value; a second multiplier for multiplying a second tap coefficient set by the tap coefficient register module and an input signal to output a result of multiplication; a first adder for adding the value output from the delayer situated upstream to the value output from the second multiplier to output a result of addition; a second delayer for delaying the value output from the first adder by a predetermined time to output the delayed value; and a selector for selecting one of the input signal, the value output from the first delayer, and the value output from the second delayer to output the selected one.

摘要翻译： 提供了一种横向滤波器，其中延迟器和乘法器串联连接，包括：用于将由抽头系数寄存器模块设置的第一抽头系数与输入信号相乘以输出乘法结果的第一乘法器; 第一延迟器，用于将从第一乘法器输出的值延迟预定时间以输出延迟值; 用于将由抽头系数寄存器模块设置的第二抽头系数与输入信号相乘以输出乘法结果的第二乘法器; 第一加法器，用于将从位于上游的延迟器输出的值相加于从第二乘法器输出的值，以输出相加结果; 第二延迟器，用于将从第一加法器输出的值延迟预定时间以输出延迟值; 以及选择器，用于选择输入信号之一，从第一延迟器输出的值和从第二延迟器输出的值以输出所选择的输入信号。

公开(公告)号：US20130064115A1

公开(公告)日：2013-03-14

申请号：US13586076

申请日：2012-08-15

申请人： HIDEHIRO TOYODA ,  Masashi Kono

发明人： HIDEHIRO TOYODA ,  Masashi Kono

IPC分类号： H04L12/26 ,  H04L29/04

CPC分类号： H04L12/26 ,  H03K17/00 ,  H03L7/081 ,  H03L7/1976 ,  H04B1/00 ,  H04J3/00 ,  H04J3/047 ,  H04J3/062 ,  H04J3/0685 ,  H04L29/04 ,  H04L43/00

摘要： Digital signals having respective pieces of frequency information different from each other are bundled, and transmitted at high speed. On receiving side, digital signals retaining the respective pieces of frequency information are recovered and separated. Transmitter apparatus divides pieces of transmission data that have the different pieces of frequency information and correspond to respective input channels into data blocks having a fixed length, as valid data, and subsequently multiplexes the data blocks corresponding to the respective input channels and outputs the multiplexed data to a transmission path. A receiver apparatus divides data string received into data flows and subsequently restores the transmission data, from the data blocks consecutive in each data flow and stores the restored data, and outputs transmission data corresponding to the respective data flows in synchronization with clocks generated for these data flows.

摘要翻译： 具有彼此不同的各个频率信息的数字信号被捆扎，并以高速发送。 在接收侧，保存各个频率信息的数字信号被恢复和分离。 发射机设备将具有不同频率信息的传输数据片段与对应于输入信道的传输数据分成具有固定长度的数据块作为有效数据，然后将与各个输入信道相对应的数据块多路复用，并输出多路复用数据 到传输路径。 接收机设备将接收到的数据串分成数据流，然后从每个数据流中连续的数据块中恢复发送数据，并存储恢复的数据，并且与为这些数据生成的时钟同步地输出与各个数据流对应的发送数据 流动。

公开(公告)号：US08090269B2

公开(公告)日：2012-01-03

申请号：US12007846

申请日：2008-01-16

申请人： Hidehiro Toyoda ,  Kenro Sekine ,  Shinya Sasaki ,  Shinji Nishimura

发明人： Hidehiro Toyoda ,  Kenro Sekine ,  Shinya Sasaki ,  Shinji Nishimura

IPC分类号： H04B10/04

CPC分类号： H04B10/5561 ,  H04B10/5055 ,  H04B10/677

摘要： A data transmission system comprising a transmitter and a receiver. The transmitter comprises a phase encoder for partitioning consecutive bit data to be input in data in units of X bits; and converting a 2x value indicated by the data of X bits in unique association with an (N/2−1)Y value of a Y symbol, and for confining use of signal points, from among the signal points of N-ary phase, only to a signal point P1 (at a phase angle 0) and N/2−2 signal points P(2n+2) (where 1≦n

摘要翻译： 一种包括发射机和接收机的数据传输系统。 发射机包括相位编码器，用于分割以X位为单位输入数据的连续位数据; 并且将由X位的数据指示的2x值与Y符号的（N / 2-1）Y值唯一相关联，并且为了限制使用信号点，从N阶相位的信号点中， 只有信号点P1（相位角0）和N / 2-2信号点P（2n + 2）（其中1＆nlE; n

公开(公告)号：US20100246389A1

公开(公告)日：2010-09-30

申请号：US12716451

申请日：2010-03-03

申请人： Hidehiro Toyoda ,  Shinji Murai

发明人： Hidehiro Toyoda ,  Shinji Murai

IPC分类号： G01R31/08

CPC分类号： H04L43/065 ,  H04L1/20 ,  H04L41/0677

摘要： It is provided a data transmission system comprising a transmitter, a repeater and a receiver. The transmitter and the repeater are coupled through a first transmission path and the receiver and the repeater are coupled through a second transmission path. The transmitter, the repeater and the receiver have virtual lanes. The transmitter demultiplexes the transmission data into as many data streams as a number of useable virtual lanes based on useable lane information. The repeater monitors failures of the transmission lanes of the first transmission path and the virtual lanes. The receiver monitors failures of the transmission lanes of the second transmission path and the virtual lanes, selects the useable virtual lanes, sends to the transmitter the useable lane information, corrects a wrong order of the received data streams and a shift of reception point in the virtual lanes, and restores the demultiplexed data streams into the transmission data.

摘要翻译： 提供了一种包括发射机，中继器和接收机的数据传输系统。 发射机和中继器通过第一传输路径耦合，并且接收机和中继器通过第二传输路径耦合。 发射机，中继器和接收机都有虚拟通道。 发射机基于可用的车道信息将传输数据解复用成与许多可用的虚拟车道一样多的数据流。 中继器监视第一传输路径和虚拟通道的传输通道的故障。 接收机监视第二传输路径和虚拟通道的传输通道的故障，选择可用的虚拟通道，向发射机发送可用的车道信息，校正接收到的数据流的错误顺序和接收点的移位 虚拟通道，并将解复用的数据流恢复为传输数据。

公开(公告)号：US20080240729A1

公开(公告)日：2008-10-02

申请号：US12007846

申请日：2008-01-16

申请人： Hidehiro Toyoda ,  Kenro Sekine ,  Shinya Sasaki ,  Shinji Nishimura

发明人： Hidehiro Toyoda ,  Kenro Sekine ,  Shinya Sasaki ,  Shinji Nishimura

IPC分类号： H04B10/00

CPC分类号： H04B10/5561 ,  H04B10/5055 ,  H04B10/677

摘要： A data transmission system comprising a transmitter and a receiver. The transmitter comprises a phase encoder for partitioning consecutive bit data to be input in data in units of X bits; and converting a 2x value indicated by the data of X bits in unique association with an (N/2-1)Y value of a Y symbol, and for confining use of signal points, from among the signal points of N-ary phase, only to a signal point P1 (at a phase angle 0) and N/2-2 signal points P(2n+2) (where 1≦n

摘要翻译： 一种数据传输系统，包括发射机和接收机。 发射机包括相位编码器，用于分割以X位为单位输入数据的连续位数据; 并且将由X位的数据指示的2×SUP值转换为与Y符号的（N / 2-1）“Y”值唯一关联，并限制使用 的信号点从N相相位的信号点仅到信号点P 1（相位角0）和N / 2-2信号点P（2n + 2）（其中1 <= n < N / 2-2）。 接收机包括相位解码器，用于当接收到不同于允许使用的信号点的信号点时通知错误检测，并且通过将信号点改变为具有较小汉明距离的信号点来进行纠错。